| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1718 case ARMISD::VCVTL: return "ARMISD::VCVTL"; in getTargetNodeName()
7358 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
15580 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| H A D | ARMInstrMVE.td | 4928 def MVEvcvtl : SDNode<"ARMISD::VCVTL", SDTARMVCVTL>;
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1716 case ARMISD::VCVTL: return "ARMISD::VCVTL"; in getTargetNodeName()
7362 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
15236 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| H A D | ARMInstrMVE.td | 4788 def MVEvcvtl : SDNode<"ARMISD::VCVTL", SDTARMVCVTL>;
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1725 case ARMISD::VCVTL: return "ARMISD::VCVTL"; in getTargetNodeName()
7344 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
15634 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1716 case ARMISD::VCVTL: return "ARMISD::VCVTL"; in getTargetNodeName()
7362 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
15239 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| H A D | ARMInstrMVE.td | 4788 def MVEvcvtl : SDNode<"ARMISD::VCVTL", SDTARMVCVTL>;
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1725 case ARMISD::VCVTL: return "ARMISD::VCVTL"; in getTargetNodeName()
7344 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
15634 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1728 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7528 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16689 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1728 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7528 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16689 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1728 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7528 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16689 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1741 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7584 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16978 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1728 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7528 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16689 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 220 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes enumerator
|
| H A D | ARMISelLowering.cpp | 1728 MAKE_CASE(ARMISD::VCVTL) in getTargetNodeName()
7528 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0, in LowerBuildVectorOfFPExt()
16689 SDValue FPExt = DAG.getNode(ARMISD::VCVTL, DL, MVT::v4f32, LoadBC, in PerformSplittingToWideningLoad()
|