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Searched refs:VLD2DUP (Results 1 – 25 of 71) sorted by relevance

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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h238 VLD2DUP, in decode_slice()
H A DARMInstrNEON.td1494 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1495 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1504 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1506 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1508 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1514 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1516 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1518 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h259 VLD2DUP, enumerator
H A DARMInstrNEON.td1465 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1466 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1475 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1477 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1479 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1485 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1487 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1489 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelLowering.h259 VLD2DUP, enumerator
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h259 VLD2DUP, enumerator
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h248 VLD2DUP, enumerator
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h239 VLD2DUP, enumerator
H A DARMInstrNEON.td1494 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1495 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1504 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1506 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1508 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1514 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1516 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1518 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.h302 VLD2DUP, enumerator
H A DARMInstrNEON.td1447 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1448 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1457 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1459 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1461 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1467 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1469 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1471 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMISelLowering.h288 VLD2DUP, enumerator
H A DARMInstrNEON.td1461 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1462 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1471 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1473 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1475 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1481 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1483 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1485 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h302 VLD2DUP, enumerator
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h288 VLD2DUP, enumerator
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h302 VLD2DUP, enumerator
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h325 VLD2DUP, enumerator
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/ARM/
H A DARMInstrNEON.td1494 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1495 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1504 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1506 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1508 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1514 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1516 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1518 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/
H A DARMInstrNEON.td1494 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1495 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1504 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1506 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1508 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1514 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1516 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1518 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/ARM/
H A DARMInstrNEON.td1494 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1495 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1504 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1506 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1508 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1514 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1516 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1518 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,

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