/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 146 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1619 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5518 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5526 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6104 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 13816 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 14008 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 15037 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 146 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1619 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5518 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5526 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6104 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 13816 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 14008 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 15037 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 146 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1619 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5518 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5526 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6104 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 13816 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 14008 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 15037 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 147 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1513 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5148 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5156 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5735 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 12683 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 12875 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 13654 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 149 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1681 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5761 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5769 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6293 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 15232 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 15490 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 16778 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 149 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1679 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5765 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5773 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6297 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 14889 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 15147 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 16416 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 149 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1688 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5747 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5755 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6279 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 15286 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 15544 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 16832 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 149 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1679 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5765 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5773 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6297 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 14892 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 15150 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 16419 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 149 VSHLIMM, // ...left enumerator
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H A D | ARMISelLowering.cpp | 1688 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM"; in getTargetNodeName() 5747 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 5755 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN() 6279 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in LowerShift() 15286 VShiftOpc = ARMISD::VSHLIMM; in PerformIntrinsicCombine() 15544 return DAG.getNode(ARMISD::VSHLIMM, dl, VT, N->getOperand(0), in PerformShiftCombine() 16832 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM)) in isVectorLoadExtDesirable()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 155 VSHLIMM, // ...left enumerator
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
H A D | ARMGenFastISel.inc | 6149 // FastEmit functions for ARMISD::VSHLIMM. 6514 case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri(VT, RetVT, Op0, Op0IsKill, imm1); 6720 // FastEmit functions for ARMISD::VSHLIMM. 6797 …case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_7(VT, RetVT, Op0, Op0IsKill… 7130 // FastEmit functions for ARMISD::VSHLIMM. 7206 …case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_31(VT, RetVT, Op0, Op0IsKil… 7684 // FastEmit functions for ARMISD::VSHLIMM. 7742 …case ARMISD::VSHLIMM: return fastEmit_ARMISD_VSHLIMM_ri_Predicate_imm0_15(VT, RetVT, Op0, Op0IsKil…
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