/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/ |
H A D | b200_core.v | 31 input bus_rst, port 91 if (bus_rst) 128 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), 151 (.clk(bus_clk), .reset(bus_rst), .clear(1'b0), 234 (.clock(bus_clk), .reset(bus_rst), 265 (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), 277 (.clk(bus_clk), .reset(bus_rst),.clear(1'b0), 316 .bus_clk(bus_clk), .bus_rst(bus_rst), 348 .bus_clk(bus_clk), .bus_rst(bus_rst), 389 .reset(bus_rst), [all …]
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H A D | b200.v | 174 wire gpif_rst, bus_rst, radio_rst; net 176 reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); 286 .bus_clk(bus_clk), .bus_rst(bus_rst), 351 .fifo_clk(bus_clk), .fifo_rst(bus_rst),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/ |
H A D | b205_core.v | 29 input bus_rst, port 79 if (bus_rst) 114 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 135 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 166 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 173 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 184 .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 190 .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 196 .clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 202 .clock(bus_clk), .reset(bus_rst), [all …]
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H A D | b205.v | 139 wire bus_rst, ref_pll_rst, radio_rst; net 140 reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst)); 252 .bus_clk(bus_clk), .bus_rst(bus_rst), 284 .gpif_clk(bus_clk), .gpif_rst(bus_rst), .gpif_enb(1'b1), 289 .fifo_clk(bus_clk), .fifo_rst(bus_rst),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_pcie_int.v | 34 input bus_rst, port 148 .reset(bus_rst), 153 .reset(bus_rst), 185 .clk(bus_clk), .reset(bus_rst), 211 .clk(bus_clk), .reset(bus_rst), 221 .clk(bus_clk), .reset(bus_rst), 233 .clk(bus_clk), .reset(bus_rst), 259 .reset(bus_rst), 293 .clk(bus_clk), .reset(bus_rst), .clear(|(dmatx_clear)), 307 .clk(bus_clk), .reset(bus_rst), .clear(|(dmatx_clear)), [all …]
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H A D | x300_sfpp_io_core.v | 20 input bus_rst, port 84 .reset(bus_rst), 173 .sys_rst(bus_rst), 362 .sys_clk(bus_clk), .sys_rst(bus_rst), 400 if (bus_rst | mac_clear) begin 416 .wb_clk(bus_clk), .wb_rst(bus_rst), 423 .wb_clk(bus_clk), .wb_rst(bus_rst), 429 .clk(bus_clk), .rst(bus_rst), 454 if (bus_rst | mac_clear) begin 502 .rst(bus_rst | ~link_up),
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H A D | x300.v | 247 wire global_rst, radio_rst, bus_rst, bus_rst_div2, ce_rst, adc_idlyctrl_rst; net 407 .reset_out(bus_rst) 446 .rst(bus_rst), 779 .bus_rst(bus_rst), 847 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 853 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 979 .bus_rst(bus_rst), 1059 .bus_rst(bus_rst), 1282 .clk(bus_clk), .xadc_clk(ioport2_clk), .rst(bus_rst), 1331 .bus_clk(bus_clk), .bus_rst(bus_rst), .sw_rst(sw_rst),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/ |
H A D | eth_internal.v | 23 input wire bus_rst, port 149 .clk(bus_clk), .reset(bus_rst), 246 .reset(bus_rst), 262 .reset(bus_rst), 284 .reset (bus_rst), 328 .aresetn (~bus_rst), 369 if (bus_rst) begin 425 .rst(bus_rst | ~link_up),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/sim/dram_fifo/ |
H A D | dram_fifo_tb.sv | 27 `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert 40 .reset(bus_rst), 64 .bus_rst(bus_rst), 100 while (bus_rst) @(posedge bus_clk); 102 `TEST_CASE_DONE((~bus_rst & ~sys_rst));
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ |
H A D | e31x_idle.v | 68 wire bus_rst; net 110 .reset_out(bus_rst) 145 pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS}; 158 onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB}; 166 if (bus_rst) begin 283 .bus_rstn(~bus_rst),
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H A D | e31x.v | 164 wire bus_rst; net 286 .reset_out(bus_rst) 348 pps_reg <= bus_rst ? 3'b000 : {pps_reg[1:0], GPS_PPS}; 361 onswitch_edge <= bus_rst ? 2'b00 : {onswitch_edge[0], ONSWITCH_DB}; 369 if (bus_rst) begin 405 .bus_rst (bus_rst), 576 .bus_rstn(~bus_rst), 687 .areset(bus_rst), 715 assign CAT_RESET = ~bus_rst; // Operates active-low, really CAT_RESET_B 851 .bus_rst(bus_rst),
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H A D | e31x_core.v | 36 input wire bus_rst, port 187 if (bus_rst) 313 .ctrlport_rst (bus_rst), 345 if (bus_rst) begin 671 .core_arst (bus_rst ),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo/ |
H A D | dram_fifo_tb.sv | 24 `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert 36 .bus_rst(bus_rst), 73 while (bus_rst) @(posedge bus_clk); 75 `TEST_CASE_DONE((~bus_rst & sys_rst_n));
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
H A D | n3xx_mgt_io_core.v | 25 input bus_rst, port 113 .reset(bus_rst), 156 if (bus_rst) begin 224 .clk(bus_clk), .reset(bus_rst), 243 .rst (bus_rst), 325 .sys_rst(bus_rst), 532 .sys_clk(bus_clk), .sys_rst(bus_rst), 590 if (bus_rst | mac_clear) begin 647 .rst(bus_rst | ~link_up),
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H A D | n3xx_sfp_wrapper.v | 26 input bus_rst, port 224 .clk(bus_clk), .reset(bus_rst), 251 .bus_rst (bus_rst), 439 .reset (bus_rst),
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H A D | e320.v | 225 wire bus_rst; net 482 .reset_out(bus_rst) 667 .sys_rst (bus_rst) 677 .rst (bus_rst), 873 assign XCVR_RESET_N = ~bus_rst; 1071 .areset(bus_rst), 1076 .bus_rst(bus_rst), 1296 .reset(bus_rst), 1318 .bus_rst (bus_rst), 1631 .bus_rstn(~bus_rst), [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
H A D | n3xx_mgt_io_core.v | 26 input bus_rst, port 126 .reset(bus_rst), 169 if (bus_rst) begin 237 .clk(bus_clk), .reset(bus_rst), 256 .rst (bus_rst), 378 .sys_rst(bus_rst), 681 .sys_clk(bus_clk), .sys_rst(bus_rst), 746 if (bus_rst | mac_clear) begin 808 .rst(bus_rst | ~link_up),
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H A D | n3xx_mgt_wrapper.v | 27 input wire bus_rst, port 159 .clk(bus_clk), .reset(bus_rst), 190 .bus_rst (bus_rst), 410 .reset (bus_rst),
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H A D | n3xx_mgt_channel_wrapper.v | 28 input wire bus_rst, port 252 .clk(bus_clk), .reset(bus_rst), 282 .bus_rst (bus_rst),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/ |
H A D | dram_fifo_bist_tb.sv | 24 `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert 55 .bus_rst(bus_rst), 96 while (bus_rst) @(posedge bus_clk); 98 `TEST_CASE_DONE(~bus_rst & sys_rst_n);
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/sim/dram_fifo_bist/ |
H A D | dram_fifo_bist_tb.sv | 28 `DEFINE_RESET(bus_rst, 0, 100) //100ns for GSR to deassert 61 .bus_rst(bus_rst), 100 while (bus_rst) @(posedge bus_clk); 102 `TEST_CASE_DONE(~bus_rst & ~sys_rst);
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/ |
H A D | eth_ipv4_interface.sv | 46 input logic bus_rst, port 113 if (bus_rst) begin 157 if (bus_rst) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
H A D | noc_traffic_counter.v | 11 input bus_clk, input bus_rst, port 69 .reset(bus_rst), .i_aclk(bus_clk), 75 .clk(bus_clk), .rst(bus_rst), .strobe(set_stb_bclk), .addr(set_addr_bclk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/ |
H A D | n3xx.v | 730 wire bus_rst; net 785 .reset_out(bus_rst) 1177 .bus_rst (bus_rst), 1376 .bus_rst (bus_rst), 1433 .bus_rst (bus_rst), 1692 .bus_rst(bus_rst), 1864 .bus_rst(bus_rst), 2299 .reset(bus_rst), 2544 .reset(bus_rst), 2567 .bus_rst (bus_rst), [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/ |
H A D | n3xx.v | 717 wire bus_rst; net 774 .reset_out(bus_rst) 1167 .bus_rst (bus_rst), 1366 .bus_rst (bus_rst), 1423 .bus_rst (bus_rst), 1683 .bus_rst(bus_rst), 1855 .bus_rst(bus_rst), 2290 .reset(bus_rst), 2535 .reset(bus_rst), 2558 .bus_rst (bus_rst), [all …]
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