1/////////////////////////////////////////////////////////////////// 2/// 3// Copyright 2018-2019 Ettus Research, A National Instruments Brand 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7// Module: n3xx 8// Description: 9// Top Level for N320, N321 devices 10// 11////////////////////////////////////////////////////////////////////// 12 13module n3xx ( 14 inout [11:0] FPGA_GPIO, 15 16 input FPGA_REFCLK_P, 17 input FPGA_REFCLK_N, 18 input REF_1PPS_IN, 19 input NETCLK_REF_P, 20 input NETCLK_REF_N, 21 //input REF_1PPS_IN_MGMT, 22 output REF_1PPS_OUT, 23 24 //TDC 25 inout UNUSED_PIN_TDCA_0, 26 inout UNUSED_PIN_TDCA_1, 27 inout UNUSED_PIN_TDCA_2, 28 inout UNUSED_PIN_TDCA_3, 29 inout UNUSED_PIN_TDCB_0, 30 inout UNUSED_PIN_TDCB_1, 31 inout UNUSED_PIN_TDCB_2, 32 inout UNUSED_PIN_TDCB_3, 33 34`ifdef NPIO_LANES 35 input NPIO_RX0_P, 36 input NPIO_RX0_N, 37 output NPIO_TX0_P, 38 output NPIO_TX0_N, 39 input NPIO_RX1_P, 40 input NPIO_RX1_N, 41 output NPIO_TX1_P, 42 output NPIO_TX1_N, 43`endif 44`ifdef QSFP_LANES 45 input [`QSFP_LANES-1:0] QSFP_RX_P, 46 input [`QSFP_LANES-1:0] QSFP_RX_N, 47 output [`QSFP_LANES-1:0] QSFP_TX_P, 48 output [`QSFP_LANES-1:0] QSFP_TX_N, 49 output QSFP_RESET_B, 50 output QSFP_LED, 51 output QSFP_MODSEL_B, 52 output QSFP_LPMODE, 53 input QSFP_PRESENT_B, 54 input QSFP_INT_B, 55 inout QSFP_I2C_SCL, 56 inout QSFP_I2C_SDA, 57`endif 58 //TODO: Uncomment when connected here 59 //input NPIO_0_RXSYNC_0_P, NPIO_0_RXSYNC_1_P, 60 //input NPIO_0_RXSYNC_0_N, NPIO_0_RXSYNC_1_N, 61 //output NPIO_0_TXSYNC_0_P, NPIO_0_TXSYNC_1_P, 62 //output NPIO_0_TXSYNC_0_N, NPIO_0_TXSYNC_1_N, 63 //input NPIO_1_RXSYNC_0_P, NPIO_1_RXSYNC_1_P, 64 //input NPIO_1_RXSYNC_0_N, NPIO_1_RXSYNC_1_N, 65 //output NPIO_1_TXSYNC_0_P, NPIO_1_TXSYNC_1_P, 66 //output NPIO_1_TXSYNC_0_N, NPIO_1_TXSYNC_1_N, 67 //input NPIO_2_RXSYNC_0_P, NPIO_2_RXSYNC_1_P, 68 //input NPIO_2_RXSYNC_0_N, NPIO_2_RXSYNC_1_N, 69 //output NPIO_2_TXSYNC_0_P, NPIO_2_TXSYNC_1_P, 70 //output NPIO_2_TXSYNC_0_N, NPIO_2_TXSYNC_1_N, 71 72 //GPS 73 input GPS_1PPS, 74 //input GPS_1PPS_RAW, 75 76 //Misc 77 input ENET0_CLK125, 78 //inout ENET0_PTP, 79 //output ENET0_PTP_DIR, 80 //inout ATSHA204_SDA, 81 input FPGA_PL_RESETN, // TODO: Add to reset logic 82 // output reg [1:0] FPGA_TEST, 83 //input PWR_CLK_FPGA, // TODO: check direction 84 input FPGA_PUDC_B, 85 86 //White Rabbit 87 input WB_20MHZ_P, 88 input WB_20MHZ_N, 89 output WB_DAC_DIN, 90 output WB_DAC_NCLR, 91 output WB_DAC_NLDAC, 92 output WB_DAC_NSYNC, 93 output WB_DAC_SCLK, 94 95 //LEDS 96 output PANEL_LED_GPS, 97 output PANEL_LED_LINK, 98 output PANEL_LED_PPS, 99 output PANEL_LED_REF, 100 101 // ARM Connections (PS) 102 inout [53:0] MIO, 103 inout PS_SRSTB, 104 inout PS_CLK, 105 inout PS_PORB, 106 inout DDR_Clk, 107 inout DDR_Clk_n, 108 inout DDR_CKE, 109 inout DDR_CS_n, 110 inout DDR_RAS_n, 111 inout DDR_CAS_n, 112 inout DDR_WEB, 113 inout [2:0] DDR_BankAddr, 114 inout [14:0] DDR_Addr, 115 inout DDR_ODT, 116 inout DDR_DRSTB, 117 inout [31:0] DDR_DQ, 118 inout [3:0] DDR_DM, 119 inout [3:0] DDR_DQS, 120 inout [3:0] DDR_DQS_n, 121 inout DDR_VRP, 122 inout DDR_VRN, 123 124 125 /////////////////////////////////// 126 // 127 // High Speed SPF+ signals and clocking 128 // 129 /////////////////////////////////// 130 131 // These clock inputs must always be enabled with a buffer regardless of the build 132 // target to avoid damage to the FPGA. 133 input NETCLK_P, 134 input NETCLK_N, 135 input MGT156MHZ_CLK1_P, 136 input MGT156MHZ_CLK1_N, 137 138 input SFP_0_RX_P, input SFP_0_RX_N, 139 output SFP_0_TX_P, output SFP_0_TX_N, 140 input SFP_1_RX_P, input SFP_1_RX_N, 141 output SFP_1_TX_P, output SFP_1_TX_N, 142 143 144 /////////////////////////////////// 145 // 146 // DRAM Interface 147 // 148 /////////////////////////////////// 149 inout [31:0] ddr3_dq, // Data pins. Input for Reads, Output for Writes. 150 inout [3:0] ddr3_dqs_n, // Data Strobes. Input for Reads, Output for Writes. 151 inout [3:0] ddr3_dqs_p, 152 // 153 output [15:0] ddr3_addr, // Address 154 output [2:0] ddr3_ba, // Bank Address 155 output ddr3_ras_n, // Row Address Strobe. 156 output ddr3_cas_n, // Column address select 157 output ddr3_we_n, // Write Enable 158 output ddr3_reset_n, // SDRAM reset pin. 159 output [0:0] ddr3_ck_p, // Differential clock 160 output [0:0] ddr3_ck_n, 161 output [0:0] ddr3_cke, // Clock Enable 162 output [0:0] ddr3_cs_n, // Chip Select 163 output [3:0] ddr3_dm, // Data Mask [3] = UDM.U26, [2] = LDM.U26, ... 164 output [0:0] ddr3_odt, // On-Die termination enable. 165 // 166 input sys_clk_p, // Differential 167 input sys_clk_n, // 100MHz clock source to generate DDR3 clocking. 168 169 170 /////////////////////////////////// 171 // 172 // Supporting I/O for SPF+ interfaces 173 // (non high speed stuff) 174 // 175 /////////////////////////////////// 176 177 //SFP+ 0, Slow Speed, Bank 13 3.3V 178 input SFP_0_I2C_NPRESENT, 179 output SFP_0_LED_A, 180 output SFP_0_LED_B, 181 input SFP_0_LOS, 182 output SFP_0_RS0, 183 output SFP_0_RS1, 184 output SFP_0_TXDISABLE, 185 input SFP_0_TXFAULT, 186 187 //SFP+ 1, Slow Speed, Bank 13 3.3V 188 //input SFP_1_I2C_NPRESENT, 189 output SFP_1_LED_A, 190 output SFP_1_LED_B, 191 input SFP_1_LOS, 192 output SFP_1_RS0, 193 output SFP_1_RS1, 194 output SFP_1_TXDISABLE, 195 input SFP_1_TXFAULT, 196 197 //USRP IO A 198 output DBA_MODULE_PWR_ENABLE, 199 output DBA_RF_PWR_ENABLE, 200 201 output DBA_CPLD_PS_SPI_SCLK, 202 output DBA_CLKDIS_SPI_CS_B, 203 output DBA_CPLD_PS_SPI_CS_B, 204 output DBA_PHDAC_SPI_CS_B, 205 output DBA_CPLD_PS_SPI_MOSI, 206 input DBA_CPLD_PS_SPI_MISO, 207 208 output DBA_ATR_RX, 209 output DBA_ATR_TX, 210 output DBA_TXRX_SW_CTRL_1, 211 output DBA_TXRX_SW_CTRL_2, 212 213 output DBA_CPLD_PL_SPI_SCLK, 214 output DBA_ADC_SPI_CS_B, 215 output DBA_DAC_SPI_CS_B, 216 output DBA_TXLO_SPI_CS_B, 217 output DBA_RXLO_SPI_CS_B, 218 output DBA_LODIS_SPI_CS_B, 219 output DBA_CPLD_PL_SPI_CS_B, 220 output DBA_CPLD_PL_SPI_MOSI, 221 input DBA_CPLD_PL_SPI_MISO, 222 223 output DBA_ADC_SYNCB_P, 224 output DBA_ADC_SYNCB_N, 225 input DBA_DAC_SYNCB_P, 226 input DBA_DAC_SYNCB_N, 227 228 output DBA_CLKDIST_SYNC, 229 230 inout DBA_CPLD_JTAG_TCK, 231 inout DBA_CPLD_JTAG_TMS, 232 inout DBA_CPLD_JTAG_TDI, 233 input DBA_CPLD_JTAG_TDO, 234 235 input DBA_FPGA_CLK_P, 236 input DBA_FPGA_CLK_N, 237 238 input DBA_FPGA_SYSREF_P, 239 input DBA_FPGA_SYSREF_N, 240 241 input DBA_MGTCLK_P, 242 input DBA_MGTCLK_N, 243 244 input [3:0] DBA_RX_P, 245 input [3:0] DBA_RX_N, 246 output [3:0] DBA_TX_P, 247 output [3:0] DBA_TX_N, 248 249 output DBA_LED_RX, 250 output DBA_LED_RX2, 251 output DBA_LED_TX, 252 253 //USRP IO B 254 output DBB_MODULE_PWR_ENABLE, 255 output DBB_RF_PWR_ENABLE, 256 257 output DBB_CPLD_PS_SPI_SCLK, 258 output DBB_CLKDIS_SPI_CS_B, 259 output DBB_CPLD_PS_SPI_CS_B, 260 output DBB_PHDAC_SPI_CS_B, 261 output DBB_CPLD_PS_SPI_MOSI, 262 input DBB_CPLD_PS_SPI_MISO, 263 264 output DBB_ATR_RX, 265 output DBB_ATR_TX, 266 output DBB_TXRX_SW_CTRL_1, 267 output DBB_TXRX_SW_CTRL_2, 268 269 output DBB_CPLD_PL_SPI_SCLK, 270 output DBB_ADC_SPI_CS_B, 271 output DBB_DAC_SPI_CS_B, 272 output DBB_TXLO_SPI_CS_B, 273 output DBB_RXLO_SPI_CS_B, 274 output DBB_LODIS_SPI_CS_B, 275 output DBB_CPLD_PL_SPI_CS_B, 276 output DBB_CPLD_PL_SPI_MOSI, 277 input DBB_CPLD_PL_SPI_MISO, 278 279 output DBB_ADC_SYNCB_P, 280 output DBB_ADC_SYNCB_N, 281 input DBB_DAC_SYNCB_P, 282 input DBB_DAC_SYNCB_N, 283 284 output DBB_CLKDIST_SYNC, 285 286 inout DBB_CPLD_JTAG_TCK, 287 inout DBB_CPLD_JTAG_TMS, 288 inout DBB_CPLD_JTAG_TDI, 289 input DBB_CPLD_JTAG_TDO, 290 291 input DBB_FPGA_CLK_P, 292 input DBB_FPGA_CLK_N, 293 294 input DBB_FPGA_SYSREF_P, 295 input DBB_FPGA_SYSREF_N, 296 297 input DBB_MGTCLK_P, 298 input DBB_MGTCLK_N, 299 300 input [3:0] DBB_RX_P, 301 input [3:0] DBB_RX_N, 302 output [3:0] DBB_TX_P, 303 output [3:0] DBB_TX_N, 304 305 output DBB_LED_RX, 306 output DBB_LED_RX2, 307 output DBB_LED_TX 308); 309 310 localparam N_AXILITE_SLAVES = 4; 311 localparam REG_AWIDTH = 14; // log2(0x4000) 312 localparam QSFP_REG_AWIDTH = 17; // log2(0x20000) 313 localparam REG_DWIDTH = 32; 314 localparam FP_GPIO_OFFSET = 32; 315 localparam FP_GPIO_WIDTH = 12; 316 317 localparam NUM_RADIOS = 2; 318 localparam NUM_CHANNELS_PER_RADIO = 1; 319 localparam NUM_DBOARDS = 2; 320 localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; 321 localparam CHANNEL_WIDTH = 32; 322 323 324 // Internal connections to PS 325 // HP0 -- High Performance port 0, FPGA is the master 326 wire [31:0] S_AXI_HP0_AWADDR; 327 wire [2:0] S_AXI_HP0_AWPROT; 328 wire S_AXI_HP0_AWVALID; 329 wire S_AXI_HP0_AWREADY; 330 wire [63:0] S_AXI_HP0_WDATA; 331 wire [7:0] S_AXI_HP0_WSTRB; 332 wire S_AXI_HP0_WVALID; 333 wire S_AXI_HP0_WREADY; 334 wire [1:0] S_AXI_HP0_BRESP; 335 wire S_AXI_HP0_BVALID; 336 wire S_AXI_HP0_BREADY; 337 wire [31:0] S_AXI_HP0_ARADDR; 338 wire [2:0] S_AXI_HP0_ARPROT; 339 wire S_AXI_HP0_ARVALID; 340 wire S_AXI_HP0_ARREADY; 341 wire [63:0] S_AXI_HP0_RDATA; 342 wire [1:0] S_AXI_HP0_RRESP; 343 wire S_AXI_HP0_RVALID; 344 wire S_AXI_HP0_RREADY; 345 wire S_AXI_HP0_RLAST; 346 wire [3:0] S_AXI_HP0_ARCACHE; 347 wire [7:0] S_AXI_HP0_AWLEN; 348 wire [2:0] S_AXI_HP0_AWSIZE; 349 wire [1:0] S_AXI_HP0_AWBURST; 350 wire [3:0] S_AXI_HP0_AWCACHE; 351 wire S_AXI_HP0_WLAST; 352 wire [7:0] S_AXI_HP0_ARLEN; 353 wire [1:0] S_AXI_HP0_ARBURST; 354 wire [2:0] S_AXI_HP0_ARSIZE; 355 356 // GP0 -- General Purpose port 0, FPGA is the master 357 wire [31:0] S_AXI_GP0_AWADDR; 358 wire [2:0] S_AXI_GP0_AWPROT; 359 wire S_AXI_GP0_AWVALID; 360 wire S_AXI_GP0_AWREADY; 361 wire [31:0] S_AXI_GP0_WDATA; 362 wire [3:0] S_AXI_GP0_WSTRB; 363 wire S_AXI_GP0_WVALID; 364 wire S_AXI_GP0_WREADY; 365 wire [1:0] S_AXI_GP0_BRESP; 366 wire S_AXI_GP0_BVALID; 367 wire S_AXI_GP0_BREADY; 368 wire [31:0] S_AXI_GP0_ARADDR; 369 wire [2:0] S_AXI_GP0_ARPROT; 370 wire S_AXI_GP0_ARVALID; 371 wire S_AXI_GP0_ARREADY; 372 wire [31:0] S_AXI_GP0_RDATA; 373 wire [1:0] S_AXI_GP0_RRESP; 374 wire S_AXI_GP0_RVALID; 375 wire S_AXI_GP0_RREADY; 376 wire S_AXI_GP0_RLAST; 377 wire [3:0] S_AXI_GP0_ARCACHE; 378 wire [7:0] S_AXI_GP0_AWLEN; 379 wire [2:0] S_AXI_GP0_AWSIZE; 380 wire [1:0] S_AXI_GP0_AWBURST; 381 wire [3:0] S_AXI_GP0_AWCACHE; 382 wire S_AXI_GP0_WLAST; 383 wire [7:0] S_AXI_GP0_ARLEN; 384 wire [1:0] S_AXI_GP0_ARBURST; 385 wire [2:0] S_AXI_GP0_ARSIZE; 386 387 // HP1 -- High Performance port 1, FPGA is the master 388 wire [5:0] S_AXI_HP1_AWID; 389 wire [31:0] S_AXI_HP1_AWADDR; 390 wire [2:0] S_AXI_HP1_AWPROT; 391 wire S_AXI_HP1_AWVALID; 392 wire S_AXI_HP1_AWREADY; 393 wire [63:0] S_AXI_HP1_WDATA; 394 wire [7:0] S_AXI_HP1_WSTRB; 395 wire S_AXI_HP1_WVALID; 396 wire S_AXI_HP1_WREADY; 397 wire [1:0] S_AXI_HP1_BRESP; 398 wire S_AXI_HP1_BVALID; 399 wire S_AXI_HP1_BREADY; 400 wire [5:0] S_AXI_HP1_ARID; 401 wire [31:0] S_AXI_HP1_ARADDR; 402 wire [2:0] S_AXI_HP1_ARPROT; 403 wire S_AXI_HP1_ARVALID; 404 wire S_AXI_HP1_ARREADY; 405 wire [63:0] S_AXI_HP1_RDATA; 406 wire [1:0] S_AXI_HP1_RRESP; 407 wire S_AXI_HP1_RVALID; 408 wire S_AXI_HP1_RREADY; 409 wire S_AXI_HP1_RLAST; 410 wire [3:0] S_AXI_HP1_ARCACHE; 411 wire [7:0] S_AXI_HP1_AWLEN; 412 wire [2:0] S_AXI_HP1_AWSIZE; 413 wire [1:0] S_AXI_HP1_AWBURST; 414 wire [3:0] S_AXI_HP1_AWCACHE; 415 wire S_AXI_HP1_WLAST; 416 wire [7:0] S_AXI_HP1_ARLEN; 417 wire [1:0] S_AXI_HP1_ARBURST; 418 wire [2:0] S_AXI_HP1_ARSIZE; 419 420 // GP1 -- General Purpose port 1, FPGA is the master 421 wire [4:0] S_AXI_GP1_AWID; 422 wire [31:0] S_AXI_GP1_AWADDR; 423 wire [2:0] S_AXI_GP1_AWPROT; 424 wire S_AXI_GP1_AWVALID; 425 wire S_AXI_GP1_AWREADY; 426 wire [31:0] S_AXI_GP1_WDATA; 427 wire [3:0] S_AXI_GP1_WSTRB; 428 wire S_AXI_GP1_WVALID; 429 wire S_AXI_GP1_WREADY; 430 wire [1:0] S_AXI_GP1_BRESP; 431 wire S_AXI_GP1_BVALID; 432 wire S_AXI_GP1_BREADY; 433 wire [4:0] S_AXI_GP1_ARID; 434 wire [31:0] S_AXI_GP1_ARADDR; 435 wire [2:0] S_AXI_GP1_ARPROT; 436 wire S_AXI_GP1_ARVALID; 437 wire S_AXI_GP1_ARREADY; 438 wire [31:0] S_AXI_GP1_RDATA; 439 wire [1:0] S_AXI_GP1_RRESP; 440 wire S_AXI_GP1_RVALID; 441 wire S_AXI_GP1_RREADY; 442 wire S_AXI_GP1_RLAST; 443 wire [3:0] S_AXI_GP1_ARCACHE; 444 wire [7:0] S_AXI_GP1_AWLEN; 445 wire [2:0] S_AXI_GP1_AWSIZE; 446 wire [1:0] S_AXI_GP1_AWBURST; 447 wire [3:0] S_AXI_GP1_AWCACHE; 448 wire S_AXI_GP1_WLAST; 449 wire [7:0] S_AXI_GP1_ARLEN; 450 wire [1:0] S_AXI_GP1_ARBURST; 451 wire [2:0] S_AXI_GP1_ARSIZE; 452 453 // GP0 -- General Purpose port 0, FPGA is the slave 454 wire M_AXI_GP0_ARVALID; 455 wire M_AXI_GP0_AWVALID; 456 wire M_AXI_GP0_BREADY; 457 wire M_AXI_GP0_RREADY; 458 wire M_AXI_GP0_WVALID; 459 wire [11:0] M_AXI_GP0_ARID; 460 wire [11:0] M_AXI_GP0_AWID; 461 wire [11:0] M_AXI_GP0_WID; 462 wire [31:0] M_AXI_GP0_ARADDR; 463 wire [31:0] M_AXI_GP0_AWADDR; 464 wire [31:0] M_AXI_GP0_WDATA; 465 wire [3:0] M_AXI_GP0_WSTRB; 466 wire M_AXI_GP0_ARREADY; 467 wire M_AXI_GP0_AWREADY; 468 wire M_AXI_GP0_BVALID; 469 wire M_AXI_GP0_RLAST; 470 wire M_AXI_GP0_RVALID; 471 wire M_AXI_GP0_WREADY; 472 wire [1:0] M_AXI_GP0_BRESP; 473 wire [1:0] M_AXI_GP0_RRESP; 474 wire [31:0] M_AXI_GP0_RDATA; 475 476 // ETH DMA 477 wire M_AXI_ETH_DMA0_ARVALID; 478 wire M_AXI_ETH_DMA0_AWVALID; 479 wire M_AXI_ETH_DMA0_BREADY; 480 wire M_AXI_ETH_DMA0_RREADY; 481 wire M_AXI_ETH_DMA0_WVALID; 482 wire [11:0] M_AXI_ETH_DMA0_ARID; 483 wire [11:0] M_AXI_ETH_DMA0_AWID; 484 wire [11:0] M_AXI_ETH_DMA0_WID; 485 wire [31:0] M_AXI_ETH_DMA0_ARADDR; 486 wire [31:0] M_AXI_ETH_DMA0_AWADDR; 487 wire [31:0] M_AXI_ETH_DMA0_WDATA; 488 wire [3:0] M_AXI_ETH_DMA0_WSTRB; 489 wire M_AXI_ETH_DMA0_ARREADY; 490 wire M_AXI_ETH_DMA0_AWREADY; 491 wire M_AXI_ETH_DMA0_BVALID; 492 wire M_AXI_ETH_DMA0_RLAST; 493 wire M_AXI_ETH_DMA0_RVALID; 494 wire M_AXI_ETH_DMA0_WREADY; 495 wire [1:0] M_AXI_ETH_DMA0_BRESP; 496 wire [1:0] M_AXI_ETH_DMA0_RRESP; 497 wire [31:0] M_AXI_ETH_DMA0_RDATA; 498 wire m_axi_eth_internal_arvalid; 499 wire m_axi_eth_internal_awvalid; 500 wire m_axi_eth_internal_bready; 501 wire m_axi_eth_internal_rready; 502 wire m_axi_eth_internal_wvalid; 503 wire [31:0] m_axi_eth_internal_araddr; 504 wire [31:0] m_axi_eth_internal_awaddr; 505 wire [31:0] m_axi_eth_internal_wdata; 506 wire [3:0] m_axi_eth_internal_wstrb; 507 wire m_axi_eth_internal_arready; 508 wire m_axi_eth_internal_awready; 509 wire m_axi_eth_internal_bvalid; 510 wire m_axi_eth_internal_rvalid; 511 wire m_axi_eth_internal_wready; 512 wire [1:0] m_axi_eth_internal_bresp; 513 wire [1:0] m_axi_eth_internal_rresp; 514 wire [31:0] m_axi_eth_internal_rdata; 515 516 wire M_AXI_NET0_ARVALID; 517 wire M_AXI_NET0_AWVALID; 518 wire M_AXI_NET0_BREADY; 519 wire M_AXI_NET0_RREADY; 520 wire M_AXI_NET0_WVALID; 521 wire [11:0] M_AXI_NET0_ARID; 522 wire [11:0] M_AXI_NET0_AWID; 523 wire [11:0] M_AXI_NET0_WID; 524 wire [31:0] M_AXI_NET0_ARADDR; 525 wire [31:0] M_AXI_NET0_AWADDR; 526 wire [31:0] M_AXI_NET0_WDATA; 527 wire [3:0] M_AXI_NET0_WSTRB; 528 wire M_AXI_NET0_ARREADY; 529 wire M_AXI_NET0_AWREADY; 530 wire M_AXI_NET0_BVALID; 531 wire M_AXI_NET0_RLAST; 532 wire M_AXI_NET0_RVALID; 533 wire M_AXI_NET0_WREADY; 534 wire [1:0] M_AXI_NET0_BRESP; 535 wire [1:0] M_AXI_NET0_RRESP; 536 wire [31:0] M_AXI_NET0_RDATA; 537 538 wire M_AXI_ETH_DMA1_ARVALID; 539 wire M_AXI_ETH_DMA1_AWVALID; 540 wire M_AXI_ETH_DMA1_BREADY; 541 wire M_AXI_ETH_DMA1_RREADY; 542 wire M_AXI_ETH_DMA1_WVALID; 543 wire [11:0] M_AXI_ETH_DMA1_ARID; 544 wire [11:0] M_AXI_ETH_DMA1_AWID; 545 wire [11:0] M_AXI_ETH_DMA1_WID; 546 wire [31:0] M_AXI_ETH_DMA1_ARADDR; 547 wire [31:0] M_AXI_ETH_DMA1_AWADDR; 548 wire [31:0] M_AXI_ETH_DMA1_WDATA; 549 wire [3:0] M_AXI_ETH_DMA1_WSTRB; 550 wire M_AXI_ETH_DMA1_ARREADY; 551 wire M_AXI_ETH_DMA1_AWREADY; 552 wire M_AXI_ETH_DMA1_BVALID; 553 wire M_AXI_ETH_DMA1_RLAST; 554 wire M_AXI_ETH_DMA1_RVALID; 555 wire M_AXI_ETH_DMA1_WREADY; 556 wire [1:0] M_AXI_ETH_DMA1_BRESP; 557 wire [1:0] M_AXI_ETH_DMA1_RRESP; 558 wire [31:0] M_AXI_ETH_DMA1_RDATA; 559 560 wire M_AXI_NET1_ARVALID; 561 wire M_AXI_NET1_AWVALID; 562 wire M_AXI_NET1_BREADY; 563 wire M_AXI_NET1_RREADY; 564 wire M_AXI_NET1_WVALID; 565 wire [11:0] M_AXI_NET1_ARID; 566 wire [11:0] M_AXI_NET1_AWID; 567 wire [11:0] M_AXI_NET1_WID; 568 wire [31:0] M_AXI_NET1_ARADDR; 569 wire [31:0] M_AXI_NET1_AWADDR; 570 wire [31:0] M_AXI_NET1_WDATA; 571 wire [3:0] M_AXI_NET1_WSTRB; 572 wire M_AXI_NET1_ARREADY; 573 wire M_AXI_NET1_AWREADY; 574 wire M_AXI_NET1_BVALID; 575 wire M_AXI_NET1_RLAST; 576 wire M_AXI_NET1_RVALID; 577 wire M_AXI_NET1_WREADY; 578 wire [1:0] M_AXI_NET1_BRESP; 579 wire [1:0] M_AXI_NET1_RRESP; 580 wire [31:0] M_AXI_NET1_RDATA; 581 582 wire M_AXI_NET2_ARVALID; 583 wire M_AXI_NET2_AWVALID; 584 wire M_AXI_NET2_BREADY; 585 wire M_AXI_NET2_RREADY; 586 wire M_AXI_NET2_WVALID; 587 wire [11:0] M_AXI_NET2_ARID; 588 wire [11:0] M_AXI_NET2_AWID; 589 wire [11:0] M_AXI_NET2_WID; 590 wire [31:0] M_AXI_NET2_ARADDR; 591 wire [31:0] M_AXI_NET2_AWADDR; 592 wire [31:0] M_AXI_NET2_WDATA; 593 wire [3:0] M_AXI_NET2_WSTRB; 594 wire M_AXI_NET2_ARREADY; 595 wire M_AXI_NET2_AWREADY; 596 wire M_AXI_NET2_BVALID; 597 wire M_AXI_NET2_RLAST; 598 wire M_AXI_NET2_RVALID; 599 wire M_AXI_NET2_WREADY; 600 wire [1:0] M_AXI_NET2_BRESP; 601 wire [1:0] M_AXI_NET2_RRESP; 602 wire [31:0] M_AXI_NET2_RDATA; 603 604 wire M_AXI_XBAR_ARVALID; 605 wire M_AXI_XBAR_AWVALID; 606 wire M_AXI_XBAR_BREADY; 607 wire M_AXI_XBAR_RREADY; 608 wire M_AXI_XBAR_WVALID; 609 wire [11:0] M_AXI_XBAR_ARID; 610 wire [11:0] M_AXI_XBAR_AWID; 611 wire [11:0] M_AXI_XBAR_WID; 612 wire [31:0] M_AXI_XBAR_ARADDR; 613 wire [31:0] M_AXI_XBAR_AWADDR; 614 wire [31:0] M_AXI_XBAR_WDATA; 615 wire [3:0] M_AXI_XBAR_WSTRB; 616 wire M_AXI_XBAR_ARREADY; 617 wire M_AXI_XBAR_AWREADY; 618 wire M_AXI_XBAR_BVALID; 619 wire M_AXI_XBAR_RLAST; 620 wire M_AXI_XBAR_RVALID; 621 wire M_AXI_XBAR_WREADY; 622 wire [1:0] M_AXI_XBAR_BRESP; 623 wire [1:0] M_AXI_XBAR_RRESP; 624 wire [31:0] M_AXI_XBAR_RDATA; 625 626 wire M_AXI_JESD0_ARVALID; 627 wire M_AXI_JESD0_AWVALID; 628 wire M_AXI_JESD0_BREADY; 629 wire M_AXI_JESD0_RREADY; 630 wire M_AXI_JESD0_WVALID; 631 wire [11:0] M_AXI_JESD0_ARID; 632 wire [11:0] M_AXI_JESD0_AWID; 633 wire [11:0] M_AXI_JESD0_WID; 634 wire [31:0] M_AXI_JESD0_ARADDR; 635 wire [31:0] M_AXI_JESD0_AWADDR; 636 wire [31:0] M_AXI_JESD0_WDATA; 637 wire [3:0] M_AXI_JESD0_WSTRB; 638 wire M_AXI_JESD0_ARREADY; 639 wire M_AXI_JESD0_AWREADY; 640 wire M_AXI_JESD0_BVALID; 641 wire M_AXI_JESD0_RLAST; 642 wire M_AXI_JESD0_RVALID; 643 wire M_AXI_JESD0_WREADY; 644 wire [1:0] M_AXI_JESD0_BRESP; 645 wire [1:0] M_AXI_JESD0_RRESP; 646 wire [31:0] M_AXI_JESD0_RDATA; 647 648 wire M_AXI_JESD1_ARVALID; 649 wire M_AXI_JESD1_AWVALID; 650 wire M_AXI_JESD1_BREADY; 651 wire M_AXI_JESD1_RREADY; 652 wire M_AXI_JESD1_WVALID; 653 wire [11:0] M_AXI_JESD1_ARID; 654 wire [11:0] M_AXI_JESD1_AWID; 655 wire [11:0] M_AXI_JESD1_WID; 656 wire [31:0] M_AXI_JESD1_ARADDR; 657 wire [31:0] M_AXI_JESD1_AWADDR; 658 wire [31:0] M_AXI_JESD1_WDATA; 659 wire [3:0] M_AXI_JESD1_WSTRB; 660 wire M_AXI_JESD1_ARREADY; 661 wire M_AXI_JESD1_AWREADY; 662 wire M_AXI_JESD1_BVALID; 663 wire M_AXI_JESD1_RLAST; 664 wire M_AXI_JESD1_RVALID; 665 wire M_AXI_JESD1_WREADY; 666 wire [1:0] M_AXI_JESD1_BRESP; 667 wire [1:0] M_AXI_JESD1_RRESP; 668 wire [31:0] M_AXI_JESD1_RDATA; 669 670 // White Rabbit 671 wire wr_uart_txd; 672 wire wr_uart_rxd; 673 wire pps_wr_refclk; 674 wire wr_ref_clk; 675 676 // AXI bus from PS to WR Core 677 wire m_axi_wr_clk; 678 wire [31:0] m_axi_wr_araddr; 679 wire [0:0] m_axi_wr_arready; 680 wire [0:0] m_axi_wr_arvalid; 681 wire [31:0] m_axi_wr_awaddr; 682 wire [0:0] m_axi_wr_awready; 683 wire [0:0] m_axi_wr_awvalid; 684 wire [0:0] m_axi_wr_bready; 685 wire [1:0] m_axi_wr_bresp; 686 wire [0:0] m_axi_wr_bvalid; 687 wire [31:0] m_axi_wr_rdata; 688 wire [0:0] m_axi_wr_rready; 689 wire [1:0] m_axi_wr_rresp; 690 wire [0:0] m_axi_wr_rvalid; 691 wire [31:0] m_axi_wr_wdata; 692 wire [0:0] m_axi_wr_wready; 693 wire [3:0] m_axi_wr_wstrb; 694 wire [0:0] m_axi_wr_wvalid; 695 696 wire [63:0] ps_gpio_out; 697 wire [63:0] ps_gpio_in; 698 wire [63:0] ps_gpio_tri; 699 700 wire [15:0] IRQ_F2P; 701 wire FCLK_CLK0; 702 wire FCLK_CLK1; 703 wire FCLK_CLK2; 704 wire FCLK_CLK3; 705 wire clk100; 706 wire clk40; 707 wire meas_clk_ref; 708 wire bus_clk; 709 wire gige_refclk; 710 wire gige_refclk_bufg; 711 wire xgige_refclk; 712 wire xgige_clk156; 713 wire xgige_dclk; 714 715 wire global_rst; 716 wire radio_rst; 717 wire bus_rst; 718 wire FCLK_RESET0_N; 719 wire clk40_rst; 720 wire clk40_rstn; 721 722 wire [1:0] USB0_PORT_INDCTL; 723 wire USB0_VBUS_PWRSELECT; 724 wire USB0_VBUS_PWRFAULT; 725 726 wire ref_clk; 727 wire wr_refclk_buf; 728 wire netclk_buf; 729 wire meas_clk; 730 wire ddr3_dma_clk; 731 wire meas_clk_reset; 732 wire meas_clk_locked; 733 wire enable_ref_clk_async; 734 wire pps_radioclk1x_iob; 735 wire pps_radioclk1x; 736 wire [3:0] pps_select; 737 wire pps_out_enb; 738 wire [1:0] pps_select_sfp; 739 wire pps_refclk; 740 wire export_pps_radioclk; 741 wire radio_clk; 742 wire radio_clkB; 743 wire radio_clk_2x; 744 wire radio_clk_2xB; 745 746 wire qsfp_sda_i; 747 wire qsfp_sda_o; 748 wire qsfp_sda_t; 749 wire qsfp_scl_i; 750 wire qsfp_scl_o; 751 wire qsfp_scl_t; 752 753 ///////////////////////////////////////////////////////////////////// 754 // 755 // Resets 756 // 757 ////////////////////////////////////////////////////////////////////// 758 759 // Global synchronous reset, on the bus_clk domain. De-asserts after 85 760 // bus_clk cycles. Asserted by default. 761 por_gen por_gen(.clk(bus_clk), .reset_out(global_rst)); 762 763 // Synchronous reset for the radio_clk domain, based on the global_rst. 764 reset_sync radio_reset_gen ( 765 .clk(radio_clk), 766 .reset_in(global_rst), 767 .reset_out(radio_rst) 768 ); 769 770 // Synchronous reset for the bus_clk domain, based on the global_rst. 771 reset_sync bus_reset_gen ( 772 .clk(bus_clk), 773 .reset_in(global_rst), 774 .reset_out(bus_rst) 775 ); 776 777 778 // PS-based Resets // 779 // 780 // Synchronous reset for the clk40 domain. This is derived from the PS reset 0. 781 reset_sync clk40_reset_gen ( 782 .clk(clk40), 783 .reset_in(~FCLK_RESET0_N), 784 .reset_out(clk40_rst) 785 ); 786 // Invert for various modules. 787 assign clk40_rstn = ~clk40_rst; 788 789 790 ///////////////////////////////////////////////////////////////////// 791 // 792 // Timing 793 // 794 ////////////////////////////////////////////////////////////////////// 795 796 // Clocks from the PS 797 // 798 // These clocks appear to have BUFGs already instantiated by the ip generator. 799 // Simply rename them here for clarity. 800 // FCLK_CLK0 : 100 MHz 801 // FCLK_CLK1 : 40 MHz 802 // FCLK_CLK2 : 166.6667 MHz 803 // FCLK_CLK3 : 200 MHz 804 assign clk100 = FCLK_CLK0; 805 assign clk40 = FCLK_CLK1; 806 assign meas_clk_ref = FCLK_CLK2; 807 assign bus_clk = FCLK_CLK3; 808 809 //If bus_clk freq ever changes, update this paramter accordingly. 810 localparam BUS_CLK_RATE = 32'd200000000; //200 MHz bus_clk rate. 811 812 n3xx_clocking n3xx_clocking_i ( 813 .enable_ref_clk_async(enable_ref_clk_async), 814 .FPGA_REFCLK_P(FPGA_REFCLK_P), 815 .FPGA_REFCLK_N(FPGA_REFCLK_N), 816 .ref_clk(ref_clk), 817 .WB_20MHz_P(WB_20MHZ_P), 818 .WB_20MHz_N(WB_20MHZ_N), 819 .wr_refclk_buf(wr_refclk_buf), 820 .NETCLK_REF_P(NETCLK_REF_P), 821 .NETCLK_REF_N(NETCLK_REF_N), 822 .netclk_buf(netclk_buf), 823 .NETCLK_P(NETCLK_P), 824 .NETCLK_N(NETCLK_N), 825 .gige_refclk_buf(gige_refclk), 826 .MGT156MHZ_CLK1_P(MGT156MHZ_CLK1_P), 827 .MGT156MHZ_CLK1_N(MGT156MHZ_CLK1_N), 828 .xgige_refclk_buf(xgige_refclk), 829 .misc_clks_ref(meas_clk_ref), 830 .meas_clk(meas_clk), 831 .ddr3_dma_clk(ddr3_dma_clk), 832 .misc_clks_reset(meas_clk_reset), 833 .misc_clks_locked(meas_clk_locked), 834 .ext_pps_from_pin(REF_1PPS_IN), 835 .gps_pps_from_pin(GPS_1PPS), 836 .pps_select(pps_select), 837 .pps_refclk(pps_refclk) 838 ); 839 840 // Drive the rear panel connector with another controllable copy of the post-TDC PPS 841 // that SW can enable/disable. The user is free to hack this to be whatever 842 // they desire. Flop the PPS signal one more time in order that it can be packed into 843 // an IOB. This extra flop stage matches the additional flop inside DbCore to allow 844 // pps_radioclk1x and pps_out_radioclk to be in sync with one another. 845 synchronizer #( 846 .FALSE_PATH_TO_IN(0) 847 ) pps_export_dsync ( 848 .clk(radio_clk), .rst(1'b0), .in(pps_out_enb), .out(export_pps_radioclk) 849 ); 850 851 // The radio_clk rate is between [122.88M, 250M] for all known N3xx variants, 852 // resulting in approximately [8ns, 4ns] periods. To pulse-extend the PPS output, 853 // we create a 25 bit-wide counter, creating ~[.262s, .131s] long output high pulses, 854 // variable depending on our radio_clk rate. Create two of the same output signal 855 // in order that the PPS_OUT gets packed into an IOB for tight timing. 856 reg [24:0] pps_out_count = 'b0; 857 reg pps_out_radioclk = 1'b0; 858 reg pps_led_radioclk = 1'b0; 859 860 always @(posedge radio_clk) begin 861 if (export_pps_radioclk) begin 862 if (pps_radioclk1x_iob) begin 863 pps_out_radioclk <= 1'b1; 864 pps_led_radioclk <= 1'b1; 865 pps_out_count <= {25{1'b1}}; 866 end else begin 867 if (pps_out_count > 0) begin 868 pps_out_count <= pps_out_count - 1'b1; 869 end else begin 870 pps_out_radioclk <= 1'b0; 871 pps_led_radioclk <= 1'b0; 872 end 873 end 874 end else begin 875 pps_out_radioclk <= 1'b0; 876 pps_led_radioclk <= 1'b0; 877 end 878 end 879 // Local to output. 880 assign REF_1PPS_OUT = pps_out_radioclk; 881 assign PANEL_LED_PPS = pps_led_radioclk; 882 883 ///////////////////////////////////////////////////////////////////// 884 // 885 // SFP, QSFP and NPIO MGT Connections 886 // 887 ////////////////////////////////////////////////////////////////////// 888 wire reg_wr_req_npio; 889 wire [REG_AWIDTH-1:0] reg_wr_addr_npio; 890 wire [REG_DWIDTH-1:0] reg_wr_data_npio; 891 wire reg_rd_req_npio; 892 wire [REG_AWIDTH-1:0] reg_rd_addr_npio; 893 wire reg_rd_resp_npio, reg_rd_resp_npio0, reg_rd_resp_npio1; 894 wire [REG_DWIDTH-1:0] reg_rd_data_npio, reg_rd_data_npio0, reg_rd_data_npio1; 895 896 regport_resp_mux #( 897 .WIDTH (REG_DWIDTH), 898 .NUM_SLAVES (2) 899 ) npio_resp_mux_i( 900 .clk(bus_clk), .reset(bus_rst), 901 .sla_rd_resp({reg_rd_resp_npio0, reg_rd_resp_npio1}), 902 .sla_rd_data({reg_rd_data_npio0, reg_rd_data_npio1}), 903 .mst_rd_resp(reg_rd_resp_npio), .mst_rd_data(reg_rd_data_npio) 904 ); 905 906 //-------------------------------------------------------------- 907 // SFP/MGT Reference Clocks 908 //-------------------------------------------------------------- 909 910 // We support the HG, XG, XA, AA targets, all of which require 911 // the 156.25MHz reference clock. Instantiate it here. 912 ten_gige_phy_clk_gen xgige_clk_gen_i ( 913 .refclk_ibuf(xgige_refclk), 914 .clk156(xgige_clk156), 915 .dclk(xgige_dclk) 916 ); 917 918 wire qpllreset; 919 wire qpllreset_sfp0, qpllreset_sfp1, qpllreset_npio0, qpllreset_npio1; 920 wire qplllock; 921 wire qplloutclk; 922 wire qplloutrefclk; 923 924 // We reuse this GT_COMMON wrapper for both ethernet and Aurora because 925 // the behavior is identical 926 ten_gig_eth_pcs_pma_gt_common # ( 927 .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware 928 ) ten_gig_eth_pcs_pma_gt_common_block ( 929 .refclk(xgige_refclk), 930 .qpllreset(qpllreset), //from 2nd sfp 931 .qplllock(qplllock), 932 .qplloutclk(qplloutclk), 933 .qplloutrefclk(qplloutrefclk), 934 .qpllrefclksel(3'b101 /*GTSOUTHREFCLK0*/) 935 ); 936 937 // The quad's QPLL should reset if any of the channels request it 938 // This should never really happen because we are not changing the reference clock 939 // source for the QPLL. 940 assign qpllreset = qpllreset_sfp0 | qpllreset_sfp1 | qpllreset_npio0 | qpllreset_npio1; 941 942 // Use the 156.25MHz reference clock for Aurora 943 wire aurora_refclk = xgige_refclk; 944 wire aurora_clk156 = xgige_clk156; 945 wire aurora_init_clk = xgige_dclk; 946 947 // White Rabbit and 1GbE both use the same clocking 948`ifdef SFP0_1GBE 949 `define SFP0_WR_1GBE 950`endif 951`ifdef SFP0_WR 952 `define SFP0_WR_1GBE 953`endif 954 955`ifdef SFP0_WR_1GBE 956 // HG and WX targets require the 1GbE clock support 957 BUFG bufg_gige_refclk_i ( 958 .I(gige_refclk), 959 .O(gige_refclk_bufg) 960 ); 961 assign SFP_0_RS0 = 1'b0; 962 assign SFP_0_RS1 = 1'b0; 963`else 964 assign SFP_0_RS0 = 1'b1; 965 assign SFP_0_RS1 = 1'b1; 966`endif 967 968 // SFP 1 is always set to run at ~10Gbps rates. 969 assign SFP_1_RS0 = 1'b1; 970 assign SFP_1_RS1 = 1'b1; 971 972 // SFP port specific reference clocks 973 wire sfp0_gt_refclk, sfp1_gt_refclk; 974 wire sfp0_gb_refclk, sfp1_gb_refclk; 975 wire sfp0_misc_clk, sfp1_misc_clk; 976 977`ifdef SFP0_10GBE 978 assign sfp0_gt_refclk = xgige_refclk; 979 assign sfp0_gb_refclk = xgige_clk156; 980 assign sfp0_misc_clk = xgige_dclk; 981`endif 982`ifdef SFP0_WR_1GBE 983 assign sfp0_gt_refclk = gige_refclk; 984 assign sfp0_gb_refclk = gige_refclk_bufg; 985 assign sfp0_misc_clk = gige_refclk_bufg; 986`endif 987`ifdef SFP0_AURORA 988 assign sfp0_gt_refclk = aurora_refclk; 989 assign sfp0_gb_refclk = aurora_clk156; 990 assign sfp0_misc_clk = aurora_init_clk; 991`endif 992 993`ifdef SFP1_10GBE 994 assign sfp1_gt_refclk = xgige_refclk; 995 assign sfp1_gb_refclk = xgige_clk156; 996 assign sfp1_misc_clk = xgige_dclk; 997`endif 998`ifdef SFP1_1GBE 999 assign sfp1_gt_refclk = gige_refclk; 1000 assign sfp1_gb_refclk = gige_refclk_bufg; 1001 assign sfp1_misc_clk = gige_refclk_bufg; 1002`endif 1003`ifdef SFP1_AURORA 1004 assign sfp1_gt_refclk = aurora_refclk; 1005 assign sfp1_gb_refclk = aurora_clk156; 1006 assign sfp1_misc_clk = aurora_init_clk; 1007`endif 1008 1009 // Instantiate Aurora MMCM if either of the SFPs 1010 // or NPIOs are Aurora 1011 wire au_tx_clk; 1012 wire au_mmcm_reset; 1013 wire au_user_clk; 1014 wire au_sync_clk; 1015 wire au_mmcm_locked; 1016 wire sfp0_tx_out_clk, sfp1_tx_out_clk; 1017 wire sfp0_gt_pll_lock, sfp1_gt_pll_lock; 1018 wire npio0_tx_out_clk, npio1_tx_out_clk; 1019 wire npio0_gt_pll_lock, npio1_gt_pll_lock; 1020 1021 //NOTE: need to declare one of these defines in order to enable Aurora on 1022 //any SFP or NPIO lane. 1023`ifdef SFP1_AURORA 1024 `define SFP_AU_MMCM 1025 assign au_tx_clk = sfp1_tx_out_clk; 1026 assign au_mmcm_reset = ~sfp1_gt_pll_lock; 1027`elsif NPIO0 1028 `define SFP_AU_MMCM 1029 assign au_tx_clk = npio0_tx_out_clk; 1030 assign au_mmcm_reset = ~npio0_gt_pll_lock; 1031`elsif NPIO1 1032 `define SFP_AU_MMCM 1033 assign au_tx_clk = npio1_tx_out_clk; 1034 assign au_mmcm_reset = ~npio1_gt_pll_lock; 1035`endif 1036 1037 1038`ifdef SFP_AU_MMCM 1039 aurora_phy_mmcm au_phy_mmcm_i ( 1040 .aurora_tx_clk_unbuf(au_tx_clk), 1041 .mmcm_reset(au_mmcm_reset), 1042 .user_clk(au_user_clk), 1043 .sync_clk(au_sync_clk), 1044 .mmcm_locked(au_mmcm_locked) 1045 ); 1046`else 1047 assign au_user_clk = 1'b0; 1048 assign au_sync_clk = 1'b0; 1049 assign au_mmcm_locked = 1'b0; 1050`endif 1051 1052 //-------------------------------------------------------------- 1053 // NPIO-QSFP MGT Lanes (Example loopback config) 1054 //-------------------------------------------------------------- 1055 1056`ifdef QSFP_LANES 1057 localparam NUM_QSFP_LANES = `QSFP_LANES; 1058 1059 // QSFP wires to the ARM core and the crossbar 1060 // These will only be connected if QSFP is 2x10 GbE 1061 wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_tx_tdata_b; 1062 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tvalid_b; 1063 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tlast_b; 1064 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_tx_tready_b; 1065 wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_tx_tuser_b; 1066 wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_tx_tkeep_b; 1067 1068 wire [NUM_QSFP_LANES*64-1:0] arm_eth_qsfp_rx_tdata_b; 1069 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tvalid_b; 1070 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tlast_b; 1071 wire [NUM_QSFP_LANES-1:0] arm_eth_qsfp_rx_tready_b; 1072 wire [NUM_QSFP_LANES*4-1:0] arm_eth_qsfp_rx_tuser_b; 1073 wire [NUM_QSFP_LANES*8-1:0] arm_eth_qsfp_rx_tkeep_b; 1074 1075 wire [NUM_QSFP_LANES*64-1:0] v2e_qsfp_tdata; 1076 wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tlast; 1077 wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tvalid; 1078 wire [NUM_QSFP_LANES-1:0] v2e_qsfp_tready; 1079 1080 wire [NUM_QSFP_LANES*64-1:0] e2v_qsfp_tdata; 1081 wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tlast; 1082 wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tvalid; 1083 wire [NUM_QSFP_LANES-1:0] e2v_qsfp_tready; 1084 1085 wire [NUM_QSFP_LANES-1:0] qsfp_link_up; 1086 1087 // QSFP quad's specific reference clocks 1088 wire qsfp_gt_refclk; 1089 wire qsfp_gb_refclk; 1090 wire qsfp_misc_clk; 1091 1092 wire qsfp_qplloutclk; 1093 wire qsfp_qplloutrefclk; 1094 wire qsfp_qplllock; 1095 wire qsfp_qpllreset; 1096 1097 wire qsfp_gt_tx_out_clk; 1098 wire qsfp_gt_pll_lock; 1099 1100 wire qsfp_au_user_clk; 1101 wire qsfp_au_sync_clk; 1102 wire qsfp_au_mmcm_locked; 1103 1104 1105`ifdef QSFP_10GBE 1106 assign qsfp_gt_refclk = xgige_refclk; 1107 assign qsfp_gb_refclk = xgige_clk156; 1108 assign qsfp_misc_clk = xgige_dclk; 1109`endif 1110`ifdef QSFP_AURORA 1111 assign qsfp_gt_refclk = aurora_refclk; 1112 assign qsfp_gb_refclk = aurora_clk156; 1113 assign qsfp_misc_clk = aurora_init_clk; 1114`endif 1115 1116 // We reuse this GT_COMMON wrapper for both ethernet and Aurora because 1117 // the behavior is identical 1118 ten_gig_eth_pcs_pma_gt_common # ( 1119 .WRAPPER_SIM_GTRESET_SPEEDUP("TRUE") //Does not affect hardware 1120 ) qsfp_gt_common_block ( 1121 .refclk(xgige_refclk), 1122 .qpllreset(qsfp_qpllreset), 1123 .qplllock(qsfp_qplllock), 1124 .qplloutclk(qsfp_qplloutclk), 1125 .qplloutrefclk(qsfp_qplloutrefclk), 1126 .qpllrefclksel(3'b001 /*GTREFCLK0*/) 1127 ); 1128 1129 `ifdef QSFP_AURORA 1130 aurora_phy_mmcm aurora_phy_mmcm ( 1131 .aurora_tx_clk_unbuf(qsfp_gt_tx_out_clk), 1132 .mmcm_reset(~qsfp_gt_pll_lock), 1133 .user_clk(qsfp_au_user_clk), 1134 .sync_clk(qsfp_au_sync_clk), 1135 .mmcm_locked(qsfp_au_mmcm_locked) 1136 ); 1137 `else 1138 assign qsfp_au_user_clk = 1'b0; 1139 assign qsfp_au_sync_clk = 1'b0; 1140 assign qsfp_au_mmcm_locked = 1'b0; 1141 `endif 1142 1143 n3xx_mgt_channel_wrapper #( 1144 `ifdef QSFP_10GBE 1145 .PROTOCOL ("10GbE"), 1146 .MDIO_EN (1'b1), 1147 .MDIO_PHYADDR (5'd4), 1148 `elsif QSFP_AURORA 1149 .PROTOCOL ("Aurora"), 1150 .MDIO_EN (1'b0), 1151 `endif 1152 .LANES (NUM_QSFP_LANES), 1153 .GT_COMMON (1), 1154 .PORTNUM_BASE (4), 1155 .REG_DWIDTH (REG_DWIDTH), 1156 .REG_AWIDTH (QSFP_REG_AWIDTH) 1157 ) qsfp_wrapper_i ( 1158 .areset (global_rst), 1159 .gt_refclk (qsfp_gt_refclk), 1160 .gb_refclk (qsfp_gb_refclk), 1161 .misc_clk (qsfp_misc_clk), 1162 .user_clk (qsfp_au_user_clk), 1163 .sync_clk (qsfp_au_sync_clk), 1164 .gt_tx_out_clk_unbuf(qsfp_gt_tx_out_clk), 1165 1166 .bus_clk (bus_clk), 1167 .bus_rst (bus_rst), 1168 1169 // GT Common 1170 .qpllrefclklost (), 1171 .qplllock (qsfp_qplllock), 1172 .qplloutclk (qsfp_qplloutclk), 1173 .qplloutrefclk (qsfp_qplloutrefclk), 1174 .qpllreset (qsfp_qpllreset), 1175 1176 // Aurora MMCM 1177 .mmcm_locked (qsfp_au_mmcm_locked), 1178 .gt_pll_lock (qsfp_gt_pll_lock), 1179 1180 .txp (QSFP_TX_P), 1181 .txn (QSFP_TX_N), 1182 .rxp (QSFP_RX_P), 1183 .rxn (QSFP_RX_N), 1184 1185 .mod_present_n (QSFP_PRESENT_B), 1186 .mod_rxlos (1'b0), 1187 .mod_tx_fault (1'b0), 1188 .mod_tx_disable (), 1189 .mod_int_n (QSFP_INT_B), 1190 .mod_reset_n (QSFP_RESET_B), 1191 .mod_lpmode (QSFP_LPMODE), 1192 .mod_sel_n (QSFP_MODSEL_B), 1193 1194 // Clock and reset 1195 .s_axi_aclk (clk40), 1196 .s_axi_aresetn (clk40_rstn), 1197 // AXI4-Lite: Write address port (domain: s_axi_aclk) 1198 .s_axi_awaddr (M_AXI_NET2_AWADDR[QSFP_REG_AWIDTH-1:0]), 1199 .s_axi_awvalid (M_AXI_NET2_AWVALID), 1200 .s_axi_awready (M_AXI_NET2_AWREADY), 1201 // AXI4-Lite: Write data port (domain: s_axi_aclk) 1202 .s_axi_wdata (M_AXI_NET2_WDATA), 1203 .s_axi_wstrb (M_AXI_NET2_WSTRB), 1204 .s_axi_wvalid (M_AXI_NET2_WVALID), 1205 .s_axi_wready (M_AXI_NET2_WREADY), 1206 // AXI4-Lite: Write response port (domain: s_axi_aclk) 1207 .s_axi_bresp (M_AXI_NET2_BRESP), 1208 .s_axi_bvalid (M_AXI_NET2_BVALID), 1209 .s_axi_bready (M_AXI_NET2_BREADY), 1210 // AXI4-Lite: Read address port (domain: s_axi_aclk) 1211 .s_axi_araddr (M_AXI_NET2_ARADDR[QSFP_REG_AWIDTH-1:0]), 1212 .s_axi_arvalid (M_AXI_NET2_ARVALID), 1213 .s_axi_arready (M_AXI_NET2_ARREADY), 1214 // AXI4-Lite: Read data port (domain: s_axi_aclk) 1215 .s_axi_rdata (M_AXI_NET2_RDATA), 1216 .s_axi_rresp (M_AXI_NET2_RRESP), 1217 .s_axi_rvalid (M_AXI_NET2_RVALID), 1218 .s_axi_rready (M_AXI_NET2_RREADY), 1219 1220 // Ethernet to Vita 1221 .e2v_tdata (e2v_qsfp_tdata), 1222 .e2v_tlast (e2v_qsfp_tlast), 1223 .e2v_tvalid (e2v_qsfp_tvalid), 1224 .e2v_tready (e2v_qsfp_tready), 1225 1226 // Vita to Ethernet 1227 .v2e_tdata (v2e_qsfp_tdata), 1228 .v2e_tlast (v2e_qsfp_tlast), 1229 .v2e_tvalid (v2e_qsfp_tvalid), 1230 .v2e_tready (v2e_qsfp_tready), 1231 1232 // Ethernet to CPU 1233 .e2c_tdata (arm_eth_qsfp_rx_tdata_b), 1234 .e2c_tkeep (arm_eth_qsfp_rx_tkeep_b), 1235 .e2c_tlast (arm_eth_qsfp_rx_tlast_b), 1236 .e2c_tvalid (arm_eth_qsfp_rx_tvalid_b), 1237 .e2c_tready (arm_eth_qsfp_rx_tready_b), 1238 1239 // CPU to Ethernet 1240 .c2e_tdata (arm_eth_qsfp_tx_tdata_b), 1241 .c2e_tkeep (arm_eth_qsfp_tx_tkeep_b), 1242 .c2e_tlast (arm_eth_qsfp_tx_tlast_b), 1243 .c2e_tvalid (arm_eth_qsfp_tx_tvalid_b), 1244 .c2e_tready (arm_eth_qsfp_tx_tready_b), 1245 1246 // Sideband White Rabbit Control 1247 .wr_reset_n (1'b1), 1248 .wr_refclk (1'b0), 1249 1250 .wr_dac_sclk (), 1251 .wr_dac_din (), 1252 .wr_dac_clr_n (), 1253 .wr_dac_cs_n (), 1254 .wr_dac_ldac_n (), 1255 1256 .wr_eeprom_scl_o(), 1257 .wr_eeprom_scl_i(1'b0), 1258 .wr_eeprom_sda_o(), 1259 .wr_eeprom_sda_i(1'b0), 1260 1261 .wr_uart_rx (1'b0), 1262 .wr_uart_tx (), 1263 1264 .mod_pps (), 1265 .mod_refclk (), 1266 1267 // WR AXI Control 1268 .wr_axi_aclk (), 1269 .wr_axi_aresetn (1'b1), 1270 .wr_axi_awaddr (), 1271 .wr_axi_awvalid (), 1272 .wr_axi_awready (), 1273 .wr_axi_wdata (), 1274 .wr_axi_wstrb (), 1275 .wr_axi_wvalid (), 1276 .wr_axi_wready (), 1277 .wr_axi_bresp (), 1278 .wr_axi_bvalid (), 1279 .wr_axi_bready (), 1280 .wr_axi_araddr (), 1281 .wr_axi_arvalid (), 1282 .wr_axi_arready (), 1283 .wr_axi_rdata (), 1284 .wr_axi_rresp (), 1285 .wr_axi_rvalid (), 1286 .wr_axi_rready (), 1287 .wr_axi_rlast (), 1288 1289 .port_info (), 1290 .device_id (device_id), 1291 1292 .link_up (qsfp_link_up), 1293 .activity () 1294 ); 1295 1296 assign QSFP_I2C_SCL = qsfp_scl_t ? 1'bz : qsfp_scl_o; 1297 assign qsfp_scl_i = QSFP_I2C_SCL; 1298 assign QSFP_I2C_SDA = qsfp_sda_t ? 1'bz : qsfp_sda_o; 1299 assign qsfp_sda_i = QSFP_I2C_SDA; 1300 1301 assign QSFP_LED = |qsfp_link_up; 1302`else 1303 1304 axi_dummy #( 1305 .DEC_ERR(1'b0) 1306 ) inst_axi_dummy_qsfp ( 1307 .s_axi_aclk(bus_clk), 1308 .s_axi_areset(bus_rst), 1309 1310 .s_axi_awaddr(M_AXI_NET2_AWADDR), 1311 .s_axi_awvalid(M_AXI_NET2_AWVALID), 1312 .s_axi_awready(M_AXI_NET2_AWREADY), 1313 1314 .s_axi_wdata(M_AXI_NET2_WDATA), 1315 .s_axi_wvalid(M_AXI_NET2_WVALID), 1316 .s_axi_wready(M_AXI_NET2_WREADY), 1317 1318 .s_axi_bresp(M_AXI_NET2_BRESP), 1319 .s_axi_bvalid(M_AXI_NET2_BVALID), 1320 .s_axi_bready(M_AXI_NET2_BREADY), 1321 1322 .s_axi_araddr(M_AXI_NET2_ARADDR), 1323 .s_axi_arvalid(M_AXI_NET2_ARVALID), 1324 .s_axi_arready(M_AXI_NET2_ARREADY), 1325 1326 .s_axi_rdata(M_AXI_NET2_RDATA), 1327 .s_axi_rresp(M_AXI_NET2_RRESP), 1328 .s_axi_rvalid(M_AXI_NET2_RVALID), 1329 .s_axi_rready(M_AXI_NET2_RREADY) 1330 1331 ); 1332 1333 assign qsfp_scl_i = qsfp_scl_t ? 1'b1 : qsfp_scl_o; 1334 assign qsfp_sda_i = qsfp_sda_t ? 1'b1 : qsfp_sda_o; 1335 1336`endif 1337 1338 //-------------------------------------------------------------- 1339 // NPIO MGT Lanes (Example loopback config) 1340 //-------------------------------------------------------------- 1341 1342`ifdef NPIO_LANES 1343 1344 wire [127:0] npio_loopback_tdata; 1345 wire [1:0] npio_loopback_tvalid; 1346 wire [1:0] npio_loopback_tready; 1347 wire [1:0] npio_loopback_tlast; 1348 1349 n3xx_mgt_io_core #( 1350 .PROTOCOL ("Aurora"), 1351 .REG_BASE (14'h00), // Base offset removed by n3xx_core 1352 .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) 1353 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus 1354 .PORTNUM (8'd2), 1355 .MDIO_EN (0) 1356 ) npio_ln_0_i ( 1357 .areset (global_rst), 1358 .gt_refclk (aurora_refclk), 1359 .gb_refclk (aurora_clk156), 1360 .misc_clk (aurora_init_clk), 1361 .user_clk (au_user_clk), 1362 .sync_clk (au_sync_clk), 1363 .gt_tx_out_clk_unbuf(npio0_tx_out_clk), 1364 1365 .bus_clk (bus_clk),//clk for status reg reads to mdio interface 1366 .bus_rst (bus_rst), 1367 .qpllreset (qpllreset_npio0), 1368 .qplloutclk (qplloutclk), 1369 .qplloutrefclk (qplloutrefclk), 1370 .qplllock (qplllock), 1371 .qpllrefclklost (), 1372 1373 .rxp (NPIO_RX0_P), 1374 .rxn (NPIO_RX0_N), 1375 .txp (NPIO_TX0_P), 1376 .txn (NPIO_TX0_N), 1377 1378 .sfpp_rxlos (1'b0), 1379 .sfpp_tx_fault (1'b0), 1380 1381 //RegPort 1382 .reg_wr_req (reg_wr_req_npio), 1383 .reg_wr_addr (reg_wr_addr_npio), 1384 .reg_wr_data (reg_wr_data_npio), 1385 .reg_rd_req (reg_rd_req_npio), 1386 .reg_rd_addr (reg_rd_addr_npio), 1387 .reg_rd_resp (reg_rd_resp_npio0), 1388 .reg_rd_data (reg_rd_data_npio0), 1389 1390 //DATA (loopback mode) 1391 .s_axis_tdata (npio_loopback_tdata[63:0]), //Data to aurora core 1392 .s_axis_tuser (4'b0), 1393 .s_axis_tvalid (npio_loopback_tvalid[0]), 1394 .s_axis_tlast (npio_loopback_tlast[0]), 1395 .s_axis_tready (npio_loopback_tready[0]), 1396 .m_axis_tdata (npio_loopback_tdata[63:0]), //Data from aurora core 1397 .m_axis_tuser (), 1398 .m_axis_tvalid (npio_loopback_tvalid[0]), 1399 .m_axis_tlast (npio_loopback_tlast[0]), 1400 .m_axis_tready (npio_loopback_tready[0]), 1401 1402 .mmcm_locked (au_mmcm_locked), 1403 .gt_pll_lock (npio0_gt_pll_lock) 1404 ); 1405 1406 n3xx_mgt_io_core #( 1407 .PROTOCOL ("Aurora"), 1408 .REG_BASE (14'h40), // Base offset removed by n3xx_core 1409 .REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) 1410 .REG_AWIDTH (REG_AWIDTH), // Width of the address bus 1411 .PORTNUM (8'd3), 1412 .MDIO_EN (0) 1413 ) npio_ln_1_i ( 1414 .areset (global_rst), 1415 .gt_refclk (aurora_refclk), 1416 .gb_refclk (aurora_clk156), 1417 .misc_clk (aurora_init_clk), 1418 .user_clk (au_user_clk), 1419 .sync_clk (au_sync_clk), 1420 .gt_tx_out_clk_unbuf(npio1_tx_out_clk), 1421 1422 .bus_clk (bus_clk),//clk for status reg reads to mdio interface 1423 .bus_rst (bus_rst), 1424 .qpllreset (qpllreset_npio1), 1425 .qplloutclk (qplloutclk), 1426 .qplloutrefclk (qplloutrefclk), 1427 .qplllock (qplllock), 1428 .qpllrefclklost (), 1429 1430 .rxp (NPIO_RX1_P), 1431 .rxn (NPIO_RX1_N), 1432 .txp (NPIO_TX1_P), 1433 .txn (NPIO_TX1_N), 1434 1435 .sfpp_rxlos (1'b0), 1436 .sfpp_tx_fault (1'b0), 1437 1438 //RegPort 1439 .reg_wr_req (reg_wr_req_npio), 1440 .reg_wr_addr (reg_wr_addr_npio), 1441 .reg_wr_data (reg_wr_data_npio), 1442 .reg_rd_req (reg_rd_req_npio), 1443 .reg_rd_addr (reg_rd_addr_npio), 1444 .reg_rd_resp (reg_rd_resp_npio1), 1445 .reg_rd_data (reg_rd_data_npio1), 1446 1447 //DATA (loopback mode) 1448 .s_axis_tdata (npio_loopback_tdata[127:64]), //Data to aurora core 1449 .s_axis_tuser (4'b0), 1450 .s_axis_tvalid (npio_loopback_tvalid[1]), 1451 .s_axis_tlast (npio_loopback_tlast[1]), 1452 .s_axis_tready (npio_loopback_tready[1]), 1453 .m_axis_tdata (npio_loopback_tdata[127:64]), //Data from aurora core 1454 .m_axis_tuser (), 1455 .m_axis_tvalid (npio_loopback_tvalid[1]), 1456 .m_axis_tlast (npio_loopback_tlast[1]), 1457 .m_axis_tready (npio_loopback_tready[1]), 1458 1459 .mmcm_locked (au_mmcm_locked), 1460 .gt_pll_lock (npio1_gt_pll_lock) 1461 ); 1462 1463`else 1464 1465 assign reg_rd_resp_npio0 = 1'b0; 1466 assign reg_rd_data_npio0 = 'h0; 1467 assign reg_rd_resp_npio1 = 1'b0; 1468 assign reg_rd_data_npio1 = 'h0; 1469 assign npio0_gt_pll_lock = 1'b1; 1470 assign npio1_gt_pll_lock = 1'b1; 1471 assign qpllreset_npio0 = 1'b0; 1472 assign qpllreset_npio1 = 1'b0; 1473 1474`endif 1475 1476 1477 // ARM ethernet 0 bridge signals 1478 wire [63:0] arm_eth0_tx_tdata; 1479 wire arm_eth0_tx_tvalid; 1480 wire arm_eth0_tx_tlast; 1481 wire arm_eth0_tx_tready; 1482 wire [3:0] arm_eth0_tx_tuser; 1483 wire [7:0] arm_eth0_tx_tkeep; 1484 1485 wire [63:0] arm_eth0_tx_tdata_b; 1486 wire arm_eth0_tx_tvalid_b; 1487 wire arm_eth0_tx_tlast_b; 1488 wire arm_eth0_tx_tready_b; 1489 wire [3:0] arm_eth0_tx_tuser_b; 1490 wire [7:0] arm_eth0_tx_tkeep_b; 1491 1492 wire [63:0] arm_eth_sfp0_tx_tdata_b; 1493 wire arm_eth_sfp0_tx_tvalid_b; 1494 wire arm_eth_sfp0_tx_tlast_b; 1495 wire arm_eth_sfp0_tx_tready_b; 1496 wire [3:0] arm_eth_sfp0_tx_tuser_b; 1497 wire [7:0] arm_eth_sfp0_tx_tkeep_b; 1498 1499 wire [63:0] arm_eth0_rx_tdata; 1500 wire arm_eth0_rx_tvalid; 1501 wire arm_eth0_rx_tlast; 1502 wire arm_eth0_rx_tready; 1503 wire [3:0] arm_eth0_rx_tuser; 1504 wire [7:0] arm_eth0_rx_tkeep; 1505 1506 wire [63:0] arm_eth0_rx_tdata_b; 1507 wire arm_eth0_rx_tvalid_b; 1508 wire arm_eth0_rx_tlast_b; 1509 wire arm_eth0_rx_tready_b; 1510 wire [3:0] arm_eth0_rx_tuser_b; 1511 wire [7:0] arm_eth0_rx_tkeep_b; 1512 1513 wire [63:0] arm_eth_sfp0_rx_tdata_b; 1514 wire arm_eth_sfp0_rx_tvalid_b; 1515 wire arm_eth_sfp0_rx_tlast_b; 1516 wire arm_eth_sfp0_rx_tready_b; 1517 wire [3:0] arm_eth_sfp0_rx_tuser_b; 1518 wire [7:0] arm_eth_sfp0_rx_tkeep_b; 1519 1520 wire arm_eth0_rx_irq; 1521 wire arm_eth0_tx_irq; 1522 1523 // ARM ethernet 1 bridge signals 1524 wire [63:0] arm_eth1_tx_tdata; 1525 wire arm_eth1_tx_tvalid; 1526 wire arm_eth1_tx_tlast; 1527 wire arm_eth1_tx_tready; 1528 wire [3:0] arm_eth1_tx_tuser; 1529 wire [7:0] arm_eth1_tx_tkeep; 1530 1531 wire [63:0] arm_eth1_tx_tdata_b; 1532 wire arm_eth1_tx_tvalid_b; 1533 wire arm_eth1_tx_tlast_b; 1534 wire arm_eth1_tx_tready_b; 1535 wire [3:0] arm_eth1_tx_tuser_b; 1536 wire [7:0] arm_eth1_tx_tkeep_b; 1537 1538 wire [63:0] arm_eth_sfp1_tx_tdata_b; 1539 wire arm_eth_sfp1_tx_tvalid_b; 1540 wire arm_eth_sfp1_tx_tlast_b; 1541 wire arm_eth_sfp1_tx_tready_b; 1542 wire [3:0] arm_eth_sfp1_tx_tuser_b; 1543 wire [7:0] arm_eth_sfp1_tx_tkeep_b; 1544 1545 wire [63:0] arm_eth1_rx_tdata; 1546 wire arm_eth1_rx_tvalid; 1547 wire arm_eth1_rx_tlast; 1548 wire arm_eth1_rx_tready; 1549 wire [3:0] arm_eth1_rx_tuser; 1550 wire [7:0] arm_eth1_rx_tkeep; 1551 1552 wire [63:0] arm_eth1_rx_tdata_b; 1553 wire arm_eth1_rx_tvalid_b; 1554 wire arm_eth1_rx_tlast_b; 1555 wire arm_eth1_rx_tready_b; 1556 wire [3:0] arm_eth1_rx_tuser_b; 1557 wire [7:0] arm_eth1_rx_tkeep_b; 1558 1559 wire [63:0] arm_eth_sfp1_rx_tdata_b; 1560 wire arm_eth_sfp1_rx_tvalid_b; 1561 wire arm_eth_sfp1_rx_tlast_b; 1562 wire arm_eth_sfp1_rx_tready_b; 1563 wire [3:0] arm_eth_sfp1_rx_tuser_b; 1564 wire [7:0] arm_eth_sfp1_rx_tkeep_b; 1565 1566 wire arm_eth1_tx_irq; 1567 wire arm_eth1_rx_irq; 1568 1569 // Vita to Ethernet 1570 wire [63:0] v2e0_tdata; 1571 wire v2e0_tlast; 1572 wire v2e0_tvalid; 1573 wire v2e0_tready; 1574 1575 wire [63:0] v2e1_tdata; 1576 wire v2e1_tlast; 1577 wire v2e1_tvalid; 1578 wire v2e1_tready; 1579 1580 wire [63:0] v2e_sfp0_tdata; 1581 wire v2e_sfp0_tlast; 1582 wire v2e_sfp0_tvalid; 1583 wire v2e_sfp0_tready; 1584 1585 wire [63:0] v2e_sfp1_tdata; 1586 wire v2e_sfp1_tlast; 1587 wire v2e_sfp1_tvalid; 1588 wire v2e_sfp1_tready; 1589 1590 // Ethernet to Vita 1591 wire [63:0] e2v0_tdata; 1592 wire e2v0_tlast; 1593 wire e2v0_tvalid; 1594 wire e2v0_tready; 1595 1596 wire [63:0] e2v1_tdata; 1597 wire e2v1_tlast; 1598 wire e2v1_tvalid; 1599 wire e2v1_tready; 1600 1601 wire [63:0] e2v_sfp0_tdata; 1602 wire e2v_sfp0_tlast; 1603 wire e2v_sfp0_tvalid; 1604 wire e2v_sfp0_tready; 1605 1606 wire [63:0] e2v_sfp1_tdata; 1607 wire e2v_sfp1_tlast; 1608 wire e2v_sfp1_tvalid; 1609 wire e2v_sfp1_tready; 1610 1611 // Ethernet crossover 1612 wire [63:0] e01_tdata, e10_tdata; 1613 wire [3:0] e01_tuser, e10_tuser; 1614 wire e01_tlast, e01_tvalid, e01_tready; 1615 wire e10_tlast, e10_tvalid, e10_tready; 1616 1617 1618 // Internal Ethernet xport adapter to PS 1619 wire [63:0] h2e_tdata; 1620 wire [7:0] h2e_tkeep; 1621 wire h2e_tlast; 1622 wire h2e_tready; 1623 wire h2e_tvalid; 1624 1625 wire [63:0] e2h_tdata; 1626 wire [7:0] e2h_tkeep; 1627 wire e2h_tlast; 1628 wire e2h_tready; 1629 wire e2h_tvalid; 1630 1631 wire [63:0] m_axis_dma_tdata; 1632 wire m_axis_dma_tlast; 1633 wire m_axis_dma_tready; 1634 wire m_axis_dma_tvalid; 1635 1636 wire [63:0] s_axis_dma_tdata; 1637 wire s_axis_dma_tlast; 1638 wire s_axis_dma_tready; 1639 wire s_axis_dma_tvalid; 1640 1641 // Misc 1642 wire [31:0] sfp_port0_info; 1643 wire [31:0] sfp_port1_info; 1644 wire sfp0_link_up, sfp1_link_up; 1645 wire [15:0] device_id; 1646 1647 ///////////////////////////////////////////////////////////////////// 1648 // 1649 // SFP Wrapper 0: Network Interface (1/10G or Aurora) 1650 // 1651 ////////////////////////////////////////////////////////////////////// 1652 1653 n3xx_mgt_channel_wrapper #( 1654 .LANES(1), 1655 `ifdef SFP0_10GBE 1656 .PROTOCOL("10GbE"), 1657 .MDIO_EN(1'b1), 1658 .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file 1659 `elsif SFP0_AURORA 1660 .PROTOCOL("Aurora"), 1661 .MDIO_EN(1'b0), 1662 `elsif SFP0_1GBE 1663 .PROTOCOL("1GbE"), 1664 .MDIO_EN(1'b1), 1665 .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file 1666 `elsif SFP0_WR 1667 .PROTOCOL("WhiteRabbit"), 1668 .MDIO_EN(1'b0), 1669 `endif 1670 .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) 1671 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus 1672 .GT_COMMON(1), 1673 .PORTNUM_BASE(8'd0) 1674 ) sfp_wrapper_0 ( 1675 .areset(global_rst), 1676 .gt_refclk(sfp0_gt_refclk), 1677 .gb_refclk(sfp0_gb_refclk), 1678 .misc_clk(sfp0_misc_clk), 1679 .user_clk(au_user_clk), 1680 .sync_clk(au_sync_clk), 1681 .gt_tx_out_clk_unbuf(sfp0_tx_out_clk), 1682 1683 .bus_rst(bus_rst), 1684 .bus_clk(bus_clk), 1685 1686 .qpllreset(qpllreset_sfp0), 1687 .qplllock(qplllock), 1688 .qplloutclk(qplloutclk), 1689 .qplloutrefclk(qplloutrefclk), 1690 .qpllrefclklost(), 1691 1692 .mmcm_locked(au_mmcm_locked), 1693 .gt_pll_lock(sfp0_gt_pll_lock), 1694 1695 .txp(SFP_0_TX_P), 1696 .txn(SFP_0_TX_N), 1697 .rxp(SFP_0_RX_P), 1698 .rxn(SFP_0_RX_N), 1699 1700 .mod_present_n(SFP_0_I2C_NPRESENT), 1701 .mod_rxlos(SFP_0_LOS), 1702 .mod_tx_fault(SFP_0_TXFAULT), 1703 .mod_tx_disable(SFP_0_TXDISABLE), 1704 1705 // Clock and reset 1706 .s_axi_aclk(clk40), 1707 .s_axi_aresetn(clk40_rstn), 1708 // AXI4-Lite: Write address port (domain: s_axi_aclk) 1709 .s_axi_awaddr(M_AXI_NET0_AWADDR[REG_AWIDTH-1:0]), 1710 .s_axi_awvalid(M_AXI_NET0_AWVALID), 1711 .s_axi_awready(M_AXI_NET0_AWREADY), 1712 // AXI4-Lite: Write data port (domain: s_axi_aclk) 1713 .s_axi_wdata(M_AXI_NET0_WDATA), 1714 .s_axi_wstrb(M_AXI_NET0_WSTRB), 1715 .s_axi_wvalid(M_AXI_NET0_WVALID), 1716 .s_axi_wready(M_AXI_NET0_WREADY), 1717 // AXI4-Lite: Write response port (domain: s_axi_aclk) 1718 .s_axi_bresp(M_AXI_NET0_BRESP), 1719 .s_axi_bvalid(M_AXI_NET0_BVALID), 1720 .s_axi_bready(M_AXI_NET0_BREADY), 1721 // AXI4-Lite: Read address port (domain: s_axi_aclk) 1722 .s_axi_araddr(M_AXI_NET0_ARADDR[REG_AWIDTH-1:0]), 1723 .s_axi_arvalid(M_AXI_NET0_ARVALID), 1724 .s_axi_arready(M_AXI_NET0_ARREADY), 1725 // AXI4-Lite: Read data port (domain: s_axi_aclk) 1726 .s_axi_rdata(M_AXI_NET0_RDATA), 1727 .s_axi_rresp(M_AXI_NET0_RRESP), 1728 .s_axi_rvalid(M_AXI_NET0_RVALID), 1729 .s_axi_rready(M_AXI_NET0_RREADY), 1730 1731 // Ethernet to Vita 1732 .e2v_tdata(e2v_sfp0_tdata), 1733 .e2v_tlast(e2v_sfp0_tlast), 1734 .e2v_tvalid(e2v_sfp0_tvalid), 1735 .e2v_tready(e2v_sfp0_tready), 1736 1737 // Vita to Ethernet 1738 .v2e_tdata(v2e_sfp0_tdata), 1739 .v2e_tlast(v2e_sfp0_tlast), 1740 .v2e_tvalid(v2e_sfp0_tvalid), 1741 .v2e_tready(v2e_sfp0_tready), 1742 1743 // Ethernet to CPU 1744 .e2c_tdata(arm_eth_sfp0_rx_tdata_b), 1745 .e2c_tkeep(arm_eth_sfp0_rx_tkeep_b), 1746 .e2c_tlast(arm_eth_sfp0_rx_tlast_b), 1747 .e2c_tvalid(arm_eth_sfp0_rx_tvalid_b), 1748 .e2c_tready(arm_eth_sfp0_rx_tready_b), 1749 1750 // CPU to Ethernet 1751 .c2e_tdata(arm_eth_sfp0_tx_tdata_b), 1752 .c2e_tkeep(arm_eth_sfp0_tx_tkeep_b), 1753 .c2e_tlast(arm_eth_sfp0_tx_tlast_b), 1754 .c2e_tvalid(arm_eth_sfp0_tx_tvalid_b), 1755 .c2e_tready(arm_eth_sfp0_tx_tready_b), 1756 1757 // White Rabbit Specific 1758`ifdef SFP0_WR 1759 .wr_reset_n (~ps_gpio_out[48]), // reset for WR only 1760 .wr_refclk (wr_refclk_buf), 1761 .wr_dac_sclk (WB_DAC_SCLK), 1762 .wr_dac_din (WB_DAC_DIN), 1763 .wr_dac_clr_n (WB_DAC_NCLR), 1764 .wr_dac_cs_n (WB_DAC_NSYNC), 1765 .wr_dac_ldac_n(WB_DAC_NLDAC), 1766 .wr_eeprom_scl_o(), // storage for delay characterization 1767 .wr_eeprom_scl_i(1'b0), // temp 1768 .wr_eeprom_sda_o(), 1769 .wr_eeprom_sda_i(1'b0), // temp 1770 .wr_uart_rx(wr_uart_rxd), // to/from PS 1771 .wr_uart_tx(wr_uart_txd), 1772 .mod_pps(pps_wr_refclk), // out, reference clock and pps 1773 .mod_refclk(wr_ref_clk), 1774 // WR Slave Port to PS 1775 .wr_axi_aclk(m_axi_wr_clk), // out to PS 1776 .wr_axi_aresetn(1'b1), // in 1777 .wr_axi_awaddr(m_axi_wr_awaddr), 1778 .wr_axi_awvalid(m_axi_wr_awvalid), 1779 .wr_axi_awready(m_axi_wr_awready), 1780 .wr_axi_wdata(m_axi_wr_wdata), 1781 .wr_axi_wstrb(m_axi_wr_wstrb), 1782 .wr_axi_wvalid(m_axi_wr_wvalid), 1783 .wr_axi_wready(m_axi_wr_wready), 1784 .wr_axi_bresp(m_axi_wr_bresp), 1785 .wr_axi_bvalid(m_axi_wr_bvalid), 1786 .wr_axi_bready(m_axi_wr_bready), 1787 .wr_axi_araddr(m_axi_wr_araddr), 1788 .wr_axi_arvalid(m_axi_wr_arvalid), 1789 .wr_axi_arready(m_axi_wr_arready), 1790 .wr_axi_rdata(m_axi_wr_rdata), 1791 .wr_axi_rresp(m_axi_wr_rresp), 1792 .wr_axi_rvalid(m_axi_wr_rvalid), 1793 .wr_axi_rready(m_axi_wr_rready), 1794 .wr_axi_rlast(), 1795`else 1796 .wr_reset_n(1'b1), 1797 .wr_refclk(1'b0), 1798 .wr_eeprom_scl_i(1'b0), 1799 .wr_eeprom_sda_i(1'b0), 1800 .wr_uart_rx(1'b0), 1801`endif 1802 1803 // Misc 1804 .port_info(sfp_port0_info), 1805 .device_id(device_id), 1806 1807 // LED 1808 .link_up(sfp0_link_up), 1809 .activity(SFP_0_LED_A) 1810 ); 1811 1812 assign ps_gpio_in[60] = ps_gpio_tri[60] ? sfp0_link_up : ps_gpio_out[60]; 1813 assign SFP_0_LED_B = sfp0_link_up; 1814 1815`ifndef SFP0_WR 1816 assign WB_DAC_SCLK = 1'b0; 1817 assign WB_DAC_DIN = 1'b0; 1818 assign WB_DAC_NCLR = 1'b1; 1819 assign WB_DAC_NSYNC = 1'b1; 1820 assign WB_DAC_NLDAC = 1'b1; 1821 assign pps_wr_refclk = 1'b0; 1822 assign wr_ref_clk = 1'b0; 1823`endif 1824 1825 ///////////////////////////////////////////////////////////////////// 1826 // 1827 // SFP Wrapper 1: Network Interface (1/10G or Aurora) 1828 // 1829 ////////////////////////////////////////////////////////////////////// 1830 1831 n3xx_mgt_channel_wrapper #( 1832 .LANES(1), 1833 `ifdef SFP1_10GBE 1834 .PROTOCOL("10GbE"), 1835 .MDIO_EN(1'b1), 1836 .MDIO_PHYADDR(5'd4), // PHYADDR must match the "reg" property for PHY in DTS file 1837 `elsif SFP1_AURORA 1838 .PROTOCOL("Aurora"), 1839 .MDIO_EN(1'b0), 1840 `endif 1841 .REG_DWIDTH(REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64) 1842 .REG_AWIDTH(REG_AWIDTH), // Width of the address bus 1843 .GT_COMMON(1), 1844 .PORTNUM_BASE(8'd1) 1845 ) sfp_wrapper_1 ( 1846 .areset(global_rst), 1847 1848 .gt_refclk(sfp1_gt_refclk), 1849 .gb_refclk(sfp1_gb_refclk), 1850 .misc_clk(sfp1_misc_clk), 1851 .user_clk(au_user_clk), 1852 .sync_clk(au_sync_clk), 1853 .gt_tx_out_clk_unbuf(sfp1_tx_out_clk), 1854 1855 .bus_rst(bus_rst), 1856 .bus_clk(bus_clk), 1857 1858 .qpllreset(qpllreset_sfp1), 1859 .qplllock(qplllock), 1860 .qplloutclk(qplloutclk), 1861 .qplloutrefclk(qplloutrefclk), 1862 .qpllrefclklost(), 1863 1864 .mmcm_locked(au_mmcm_locked), 1865 .gt_pll_lock(sfp1_gt_pll_lock), 1866 1867 .txp(SFP_1_TX_P), 1868 .txn(SFP_1_TX_N), 1869 .rxp(SFP_1_RX_P), 1870 .rxn(SFP_1_RX_N), 1871 1872 .mod_rxlos(SFP_1_LOS), 1873 .mod_tx_fault(SFP_1_TXFAULT), 1874 .mod_tx_disable(SFP_1_TXDISABLE), 1875 1876 // Clock and reset 1877 .s_axi_aclk(clk40), 1878 .s_axi_aresetn(clk40_rstn), 1879 // AXI4-Lite: Write address port (domain: s_axi_aclk) 1880 .s_axi_awaddr(M_AXI_NET1_AWADDR[REG_AWIDTH-1:0]), 1881 .s_axi_awvalid(M_AXI_NET1_AWVALID), 1882 .s_axi_awready(M_AXI_NET1_AWREADY), 1883 // AXI4-Lite: Write data port (domain: s_axi_aclk) 1884 .s_axi_wdata(M_AXI_NET1_WDATA), 1885 .s_axi_wstrb(M_AXI_NET1_WSTRB), 1886 .s_axi_wvalid(M_AXI_NET1_WVALID), 1887 .s_axi_wready(M_AXI_NET1_WREADY), 1888 // AXI4-Lite: Write response port (domain: s_axi_aclk) 1889 .s_axi_bresp(M_AXI_NET1_BRESP), 1890 .s_axi_bvalid(M_AXI_NET1_BVALID), 1891 .s_axi_bready(M_AXI_NET1_BREADY), 1892 // AXI4-Lite: Read address port (domain: s_axi_aclk) 1893 .s_axi_araddr(M_AXI_NET1_ARADDR[REG_AWIDTH-1:0]), 1894 .s_axi_arvalid(M_AXI_NET1_ARVALID), 1895 .s_axi_arready(M_AXI_NET1_ARREADY), 1896 // AXI4-Lite: Read data port (domain: s_axi_aclk) 1897 .s_axi_rdata(M_AXI_NET1_RDATA), 1898 .s_axi_rresp(M_AXI_NET1_RRESP), 1899 .s_axi_rvalid(M_AXI_NET1_RVALID), 1900 .s_axi_rready(M_AXI_NET1_RREADY), 1901 1902 // Ethernet to Vita 1903 .e2v_tdata(e2v_sfp1_tdata), 1904 .e2v_tlast(e2v_sfp1_tlast), 1905 .e2v_tvalid(e2v_sfp1_tvalid), 1906 .e2v_tready(e2v_sfp1_tready), 1907 1908 // Vita to Ethernet 1909 .v2e_tdata(v2e_sfp1_tdata), 1910 .v2e_tlast(v2e_sfp1_tlast), 1911 .v2e_tvalid(v2e_sfp1_tvalid), 1912 .v2e_tready(v2e_sfp1_tready), 1913 1914 // Ethernet to CPU 1915 .e2c_tdata(arm_eth_sfp1_rx_tdata_b), 1916 .e2c_tkeep(arm_eth_sfp1_rx_tkeep_b), 1917 .e2c_tlast(arm_eth_sfp1_rx_tlast_b), 1918 .e2c_tvalid(arm_eth_sfp1_rx_tvalid_b), 1919 .e2c_tready(arm_eth_sfp1_rx_tready_b), 1920 1921 // CPU to Ethernet 1922 .c2e_tdata(arm_eth_sfp1_tx_tdata_b), 1923 .c2e_tkeep(arm_eth_sfp1_tx_tkeep_b), 1924 .c2e_tlast(arm_eth_sfp1_tx_tlast_b), 1925 .c2e_tvalid(arm_eth_sfp1_tx_tvalid_b), 1926 .c2e_tready(arm_eth_sfp1_tx_tready_b), 1927 1928 // Misc 1929 .port_info(sfp_port1_info), 1930 .device_id(device_id), 1931 1932 // LED 1933 .link_up(sfp1_link_up), 1934 .activity(SFP_1_LED_A) 1935 ); 1936 1937 assign ps_gpio_in[61] = ps_gpio_tri[61] ? sfp1_link_up : ps_gpio_out[61]; 1938 assign SFP_1_LED_B = sfp1_link_up; 1939 1940 ///////////////////////////////////////////////////////////////////// 1941 // 1942 // Ethernet DMA 0 1943 // 1944 ////////////////////////////////////////////////////////////////////// 1945 1946 assign IRQ_F2P[0] = arm_eth0_rx_irq; 1947 assign IRQ_F2P[1] = arm_eth0_tx_irq; 1948 1949 1950`ifdef QSFP_10GBE 1951 // QSFP+ lanes connect to DMA engines and crossbar 1952 // Connect first QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) 1953 assign arm_eth_qsfp_tx_tdata_b[0*64 +: 64] = arm_eth0_tx_tdata_b; 1954 assign arm_eth_qsfp_tx_tvalid_b[0] = arm_eth0_tx_tvalid_b; 1955 assign arm_eth_qsfp_tx_tlast_b[0] = arm_eth0_tx_tlast_b; 1956 assign arm_eth0_tx_tready_b = arm_eth_qsfp_tx_tready_b[0]; 1957 assign arm_eth_qsfp_tx_tuser_b[0*4 +: 4] = arm_eth0_tx_tuser_b; 1958 assign arm_eth_qsfp_tx_tkeep_b[0*8 +: 8] = arm_eth0_tx_tkeep_b; 1959 1960 assign arm_eth0_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[0*64 +: 64]; 1961 assign arm_eth0_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[0]; 1962 assign arm_eth0_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[0]; 1963 assign arm_eth_qsfp_rx_tready_b[0] = arm_eth0_rx_tready_b; 1964 assign arm_eth0_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[0*4 +: 4]; 1965 assign arm_eth0_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[0*8 +: 8]; 1966 1967 // Connect first QSFP+ 10 GbE port to the crossbar 1968 assign v2e_qsfp_tdata[0*64 +: 64] = v2e0_tdata; 1969 assign v2e_qsfp_tlast[0] = v2e0_tlast; 1970 assign v2e_qsfp_tvalid[0] = v2e0_tvalid; 1971 assign v2e0_tready = v2e_qsfp_tready[0]; 1972 1973 assign e2v0_tdata = e2v_qsfp_tdata[0*64 +: 64]; 1974 assign e2v0_tlast = e2v_qsfp_tlast[0]; 1975 assign e2v0_tvalid = e2v_qsfp_tvalid[0]; 1976 assign e2v_qsfp_tready[0] = e2v0_tready; 1977 1978 // Connect second QSFP+ 10 GbE port to a DMA engine (and the PS/ARM) 1979 assign arm_eth_qsfp_tx_tdata_b[1*64 +: 64] = arm_eth1_tx_tdata_b; 1980 assign arm_eth_qsfp_tx_tvalid_b[1] = arm_eth1_tx_tvalid_b; 1981 assign arm_eth_qsfp_tx_tlast_b[1] = arm_eth1_tx_tlast_b; 1982 assign arm_eth1_tx_tready_b = arm_eth_qsfp_tx_tready_b[1]; 1983 assign arm_eth_qsfp_tx_tuser_b[1*4 +: 4] = arm_eth1_tx_tuser_b; 1984 assign arm_eth_qsfp_tx_tkeep_b[1*8 +: 8] = arm_eth1_tx_tkeep_b; 1985 1986 assign arm_eth1_rx_tdata_b = arm_eth_qsfp_rx_tdata_b[1*64 +: 64]; 1987 assign arm_eth1_rx_tvalid_b = arm_eth_qsfp_rx_tvalid_b[1]; 1988 assign arm_eth1_rx_tlast_b = arm_eth_qsfp_rx_tlast_b[1]; 1989 assign arm_eth_qsfp_rx_tready_b[1] = arm_eth1_rx_tready_b; 1990 assign arm_eth1_rx_tuser_b = arm_eth_qsfp_rx_tuser_b[1*4 +: 4]; 1991 assign arm_eth1_rx_tkeep_b = arm_eth_qsfp_rx_tkeep_b[1*8 +: 8]; 1992 1993 // Connect second QSFP+ 10 GbE port to the crossbar 1994 assign v2e_qsfp_tdata[1*64 +: 64] = v2e1_tdata; 1995 assign v2e_qsfp_tlast[1] = v2e1_tlast; 1996 assign v2e_qsfp_tvalid[1] = v2e1_tvalid; 1997 assign v2e1_tready = v2e_qsfp_tready[1]; 1998 1999 assign e2v1_tdata = e2v_qsfp_tdata[1*64 +: 64]; 2000 assign e2v1_tlast = e2v_qsfp_tlast[1]; 2001 assign e2v1_tvalid = e2v_qsfp_tvalid[1]; 2002 assign e2v_qsfp_tready[1] = e2v1_tready; 2003`else 2004 // SFP+ ports connects to DMA engines and crossbar 2005 // Connect first SFP+ 10 GbE port to a DMA engine (and the PS/ARM) 2006 assign arm_eth_sfp0_tx_tdata_b = arm_eth0_tx_tdata_b; 2007 assign arm_eth_sfp0_tx_tvalid_b = arm_eth0_tx_tvalid_b; 2008 assign arm_eth_sfp0_tx_tlast_b = arm_eth0_tx_tlast_b; 2009 assign arm_eth0_tx_tready_b = arm_eth_sfp0_tx_tready_b; 2010 assign arm_eth_sfp0_tx_tuser_b = arm_eth0_tx_tuser_b; 2011 assign arm_eth_sfp0_tx_tkeep_b = arm_eth0_tx_tkeep_b; 2012 2013 assign arm_eth0_rx_tdata_b = arm_eth_sfp0_rx_tdata_b; 2014 assign arm_eth0_rx_tvalid_b = arm_eth_sfp0_rx_tvalid_b; 2015 assign arm_eth0_rx_tlast_b = arm_eth_sfp0_rx_tlast_b; 2016 assign arm_eth_sfp0_rx_tready_b = arm_eth0_rx_tready_b; 2017 assign arm_eth0_rx_tuser_b = arm_eth_sfp0_rx_tuser_b; 2018 assign arm_eth0_rx_tkeep_b = arm_eth_sfp0_rx_tkeep_b; 2019 2020 // Connect first SFP+ 10 GbE port to the crossbar 2021 assign v2e_sfp0_tdata = v2e0_tdata; 2022 assign v2e_sfp0_tlast = v2e0_tlast; 2023 assign v2e_sfp0_tvalid = v2e0_tvalid; 2024 assign v2e0_tready = v2e_sfp0_tready; 2025 2026 assign e2v0_tdata = e2v_sfp0_tdata; 2027 assign e2v0_tlast = e2v_sfp0_tlast; 2028 assign e2v0_tvalid = e2v_sfp0_tvalid; 2029 assign e2v_sfp0_tready = e2v0_tready; 2030 2031 // Connect second SFP+ 10 GbE port to a DMA engine (and the PS/ARM) 2032 assign arm_eth_sfp1_tx_tdata_b = arm_eth1_tx_tdata_b; 2033 assign arm_eth_sfp1_tx_tvalid_b = arm_eth1_tx_tvalid_b; 2034 assign arm_eth_sfp1_tx_tlast_b = arm_eth1_tx_tlast_b; 2035 assign arm_eth1_tx_tready_b = arm_eth_sfp1_tx_tready_b; 2036 assign arm_eth_sfp1_tx_tuser_b = arm_eth1_tx_tuser_b; 2037 assign arm_eth_sfp1_tx_tkeep_b = arm_eth1_tx_tkeep_b; 2038 2039 assign arm_eth1_rx_tdata_b = arm_eth_sfp1_rx_tdata_b; 2040 assign arm_eth1_rx_tvalid_b = arm_eth_sfp1_rx_tvalid_b; 2041 assign arm_eth1_rx_tlast_b = arm_eth_sfp1_rx_tlast_b; 2042 assign arm_eth_sfp1_rx_tready_b = arm_eth1_rx_tready_b; 2043 assign arm_eth1_rx_tuser_b = arm_eth_sfp1_rx_tuser_b; 2044 assign arm_eth1_rx_tkeep_b = arm_eth_sfp1_rx_tkeep_b; 2045 2046 // Connect first SFP+ 10 GbE port to the crossbar 2047 assign v2e_sfp1_tdata = v2e1_tdata; 2048 assign v2e_sfp1_tlast = v2e1_tlast; 2049 assign v2e_sfp1_tvalid = v2e1_tvalid; 2050 assign v2e1_tready = v2e_sfp1_tready; 2051 2052 assign e2v1_tdata = e2v_sfp1_tdata; 2053 assign e2v1_tlast = e2v_sfp1_tlast; 2054 assign e2v1_tvalid = e2v_sfp1_tvalid; 2055 assign e2v_sfp1_tready = e2v1_tready; 2056 2057 // Don't actually instantiate DMA engines if protocols can't use them 2058 `ifdef SFP0_AURORA 2059 `define NO_ETH_DMA_0 2060 `elsif SFP0_WR 2061 `define NO_ETH_DMA_0 2062 `endif 2063 2064 `ifdef SFP1_AURORA 2065 `define NO_ETH_DMA_1 2066 `endif 2067`endif 2068 2069`ifdef NO_ETH_DMA_0 2070 //If inst Aurora, tie off each axi/axi-lite interface 2071 axi_dummy #( 2072 .DEC_ERR(1'b0) 2073 ) inst_axi_dummy_sfp0_eth_dma ( 2074 .s_axi_aclk(bus_clk), 2075 .s_axi_areset(bus_rst), 2076 2077 .s_axi_awaddr(M_AXI_ETH_DMA0_AWADDR), 2078 .s_axi_awvalid(M_AXI_ETH_DMA0_AWVALID), 2079 .s_axi_awready(M_AXI_ETH_DMA0_AWREADY), 2080 2081 .s_axi_wdata(M_AXI_ETH_DMA0_WDATA), 2082 .s_axi_wvalid(M_AXI_ETH_DMA0_WVALID), 2083 .s_axi_wready(M_AXI_ETH_DMA0_WREADY), 2084 2085 .s_axi_bresp(M_AXI_ETH_DMA0_BRESP), 2086 .s_axi_bvalid(M_AXI_ETH_DMA0_BVALID), 2087 .s_axi_bready(M_AXI_ETH_DMA0_BREADY), 2088 2089 .s_axi_araddr(M_AXI_ETH_DMA0_ARADDR), 2090 .s_axi_arvalid(M_AXI_ETH_DMA0_ARVALID), 2091 .s_axi_arready(M_AXI_ETH_DMA0_ARREADY), 2092 2093 .s_axi_rdata(M_AXI_ETH_DMA0_RDATA), 2094 .s_axi_rresp(M_AXI_ETH_DMA0_RRESP), 2095 .s_axi_rvalid(M_AXI_ETH_DMA0_RVALID), 2096 .s_axi_rready(M_AXI_ETH_DMA0_RREADY) 2097 2098 ); 2099 //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off 2100 assign S_AXI_GP0_AWADDR = 32'h0; 2101 assign S_AXI_GP0_AWLEN = 8'h0; 2102 assign S_AXI_GP0_AWSIZE = 4'h0; 2103 assign S_AXI_GP0_AWBURST = 3'h0; 2104 assign S_AXI_GP0_AWPROT = 3'h0; 2105 assign S_AXI_GP0_AWCACHE = 4'h0; 2106 assign S_AXI_GP0_AWVALID = 1'b0; 2107 //S_AXI_GP0_AWREADY output from PS 2108 assign S_AXI_GP0_WDATA = 32'h0; 2109 assign S_AXI_GP0_WSTRB = 4'h0; 2110 assign S_AXI_GP0_WLAST = 1'b0; 2111 assign S_AXI_GP0_WVALID = 1'b0; 2112 //S_AXI_GP0_WREADY output from PS 2113 //S_AXI_GP0_BRESP 2114 //S_AXI_GP0_BVALID 2115 assign S_AXI_GP0_BREADY = 1'b1; 2116 assign S_AXI_GP0_ARADDR = 32'h0; 2117 assign S_AXI_GP0_ARLEN = 8'h0; 2118 assign S_AXI_GP0_ARSIZE = 3'h0; 2119 assign S_AXI_GP0_ARBURST = 2'h0; 2120 assign S_AXI_GP0_ARPROT = 3'h0; 2121 assign S_AXI_GP0_ARCACHE = 4'h0; 2122 assign S_AXI_GP0_ARVALID = 1'b0; 2123 //S_AXI_GP0_ARREADY 2124 //S_AXI_GP0_RDATA 2125 //S_AXI_GP0_RRESP 2126 //S_AXI_GP0_RLAST 2127 //S_AXI_GP0_RVALID 2128 assign S_AXI_GP0_RREADY = 1'b1; 2129 2130 //S_AXI_HP0 from axi_eth_dma 2131 assign S_AXI_HP0_ARADDR = 32'h0; 2132 assign S_AXI_HP0_ARLEN = 8'h0; 2133 assign S_AXI_HP0_ARSIZE = 3'h0; 2134 assign S_AXI_HP0_ARBURST = 2'h0; 2135 assign S_AXI_HP0_ARPROT = 3'h0; 2136 assign S_AXI_HP0_ARCACHE = 4'h0; 2137 assign S_AXI_HP0_ARVALID = 1'b0; 2138 //S_AXI_HP0_ARREADY 2139 //S_AXI_HP0_RDATA 2140 //S_AXI_HP0_RRESP 2141 //S_AXI_HP0_RLAST 2142 //S_AXI_HP0_RVALID 2143 assign S_AXI_HP0_RREADY = 1'b1; 2144 assign S_AXI_HP0_AWADDR = 32'h0; 2145 assign S_AXI_HP0_AWLEN = 8'h0; 2146 assign S_AXI_HP0_AWSIZE = 3'h0; 2147 assign S_AXI_HP0_AWBURST = 2'h0; 2148 assign S_AXI_HP0_AWPROT = 3'h0; 2149 assign S_AXI_HP0_AWCACHE = 4'h0; 2150 assign S_AXI_HP0_AWVALID = 1'b0; 2151 //S_AXI_HP0_AWREADY 2152 assign S_AXI_HP0_WDATA = 64'h0; 2153 assign S_AXI_HP0_WSTRB = 8'h0; 2154 assign S_AXI_HP0_WLAST = 1'b0; 2155 assign S_AXI_HP0_WVALID = 1'b0; 2156 //S_AXI_HP0_WREADY 2157 //S_AXI_HP0_BRESP 2158 //S_AXI_HP0_BVALID 2159 assign S_AXI_HP0_BREADY = 1'b1; 2160 2161`else 2162 2163 axi_eth_dma inst_axi_eth_dma0 ( 2164 .s_axi_lite_aclk(clk40), 2165 .m_axi_sg_aclk(clk40), 2166 .m_axi_mm2s_aclk(clk40), 2167 .m_axi_s2mm_aclk(clk40), 2168 .axi_resetn(clk40_rstn), 2169 2170 .s_axi_lite_awaddr(M_AXI_ETH_DMA0_AWADDR), 2171 .s_axi_lite_awvalid(M_AXI_ETH_DMA0_AWVALID), 2172 .s_axi_lite_awready(M_AXI_ETH_DMA0_AWREADY), 2173 2174 .s_axi_lite_wdata(M_AXI_ETH_DMA0_WDATA), 2175 .s_axi_lite_wvalid(M_AXI_ETH_DMA0_WVALID), 2176 .s_axi_lite_wready(M_AXI_ETH_DMA0_WREADY), 2177 2178 .s_axi_lite_bresp(M_AXI_ETH_DMA0_BRESP), 2179 .s_axi_lite_bvalid(M_AXI_ETH_DMA0_BVALID), 2180 .s_axi_lite_bready(M_AXI_ETH_DMA0_BREADY), 2181 2182 .s_axi_lite_araddr(M_AXI_ETH_DMA0_ARADDR), 2183 .s_axi_lite_arvalid(M_AXI_ETH_DMA0_ARVALID), 2184 .s_axi_lite_arready(M_AXI_ETH_DMA0_ARREADY), 2185 2186 .s_axi_lite_rdata(M_AXI_ETH_DMA0_RDATA), 2187 .s_axi_lite_rresp(M_AXI_ETH_DMA0_RRESP), 2188 .s_axi_lite_rvalid(M_AXI_ETH_DMA0_RVALID), 2189 .s_axi_lite_rready(M_AXI_ETH_DMA0_RREADY), 2190 2191 .m_axi_sg_awaddr(S_AXI_GP0_AWADDR), 2192 .m_axi_sg_awlen(S_AXI_GP0_AWLEN), 2193 .m_axi_sg_awsize(S_AXI_GP0_AWSIZE), 2194 .m_axi_sg_awburst(S_AXI_GP0_AWBURST), 2195 .m_axi_sg_awprot(S_AXI_GP0_AWPROT), 2196 .m_axi_sg_awcache(S_AXI_GP0_AWCACHE), 2197 .m_axi_sg_awvalid(S_AXI_GP0_AWVALID), 2198 .m_axi_sg_awready(S_AXI_GP0_AWREADY), 2199 .m_axi_sg_wdata(S_AXI_GP0_WDATA), 2200 .m_axi_sg_wstrb(S_AXI_GP0_WSTRB), 2201 .m_axi_sg_wlast(S_AXI_GP0_WLAST), 2202 .m_axi_sg_wvalid(S_AXI_GP0_WVALID), 2203 .m_axi_sg_wready(S_AXI_GP0_WREADY), 2204 .m_axi_sg_bresp(S_AXI_GP0_BRESP), 2205 .m_axi_sg_bvalid(S_AXI_GP0_BVALID), 2206 .m_axi_sg_bready(S_AXI_GP0_BREADY), 2207 .m_axi_sg_araddr(S_AXI_GP0_ARADDR), 2208 .m_axi_sg_arlen(S_AXI_GP0_ARLEN), 2209 .m_axi_sg_arsize(S_AXI_GP0_ARSIZE), 2210 .m_axi_sg_arburst(S_AXI_GP0_ARBURST), 2211 .m_axi_sg_arprot(S_AXI_GP0_ARPROT), 2212 .m_axi_sg_arcache(S_AXI_GP0_ARCACHE), 2213 .m_axi_sg_arvalid(S_AXI_GP0_ARVALID), 2214 .m_axi_sg_arready(S_AXI_GP0_ARREADY), 2215 .m_axi_sg_rdata(S_AXI_GP0_RDATA), 2216 .m_axi_sg_rresp(S_AXI_GP0_RRESP), 2217 .m_axi_sg_rlast(S_AXI_GP0_RLAST), 2218 .m_axi_sg_rvalid(S_AXI_GP0_RVALID), 2219 .m_axi_sg_rready(S_AXI_GP0_RREADY), 2220 2221 .m_axi_mm2s_araddr(S_AXI_HP0_ARADDR), 2222 .m_axi_mm2s_arlen(S_AXI_HP0_ARLEN), 2223 .m_axi_mm2s_arsize(S_AXI_HP0_ARSIZE), 2224 .m_axi_mm2s_arburst(S_AXI_HP0_ARBURST), 2225 .m_axi_mm2s_arprot(S_AXI_HP0_ARPROT), 2226 .m_axi_mm2s_arcache(S_AXI_HP0_ARCACHE), 2227 .m_axi_mm2s_arvalid(S_AXI_HP0_ARVALID), 2228 .m_axi_mm2s_arready(S_AXI_HP0_ARREADY), 2229 .m_axi_mm2s_rdata(S_AXI_HP0_RDATA), 2230 .m_axi_mm2s_rresp(S_AXI_HP0_RRESP), 2231 .m_axi_mm2s_rlast(S_AXI_HP0_RLAST), 2232 .m_axi_mm2s_rvalid(S_AXI_HP0_RVALID), 2233 .m_axi_mm2s_rready(S_AXI_HP0_RREADY), 2234 2235 .mm2s_prmry_reset_out_n(), 2236 .m_axis_mm2s_tdata(arm_eth0_tx_tdata), 2237 .m_axis_mm2s_tkeep(arm_eth0_tx_tkeep), 2238 .m_axis_mm2s_tvalid(arm_eth0_tx_tvalid), 2239 .m_axis_mm2s_tready(arm_eth0_tx_tready), 2240 .m_axis_mm2s_tlast(arm_eth0_tx_tlast), 2241 2242 .m_axi_s2mm_awaddr(S_AXI_HP0_AWADDR), 2243 .m_axi_s2mm_awlen(S_AXI_HP0_AWLEN), 2244 .m_axi_s2mm_awsize(S_AXI_HP0_AWSIZE), 2245 .m_axi_s2mm_awburst(S_AXI_HP0_AWBURST), 2246 .m_axi_s2mm_awprot(S_AXI_HP0_AWPROT), 2247 .m_axi_s2mm_awcache(S_AXI_HP0_AWCACHE), 2248 .m_axi_s2mm_awvalid(S_AXI_HP0_AWVALID), 2249 .m_axi_s2mm_awready(S_AXI_HP0_AWREADY), 2250 .m_axi_s2mm_wdata(S_AXI_HP0_WDATA), 2251 .m_axi_s2mm_wstrb(S_AXI_HP0_WSTRB), 2252 .m_axi_s2mm_wlast(S_AXI_HP0_WLAST), 2253 .m_axi_s2mm_wvalid(S_AXI_HP0_WVALID), 2254 .m_axi_s2mm_wready(S_AXI_HP0_WREADY), 2255 .m_axi_s2mm_bresp(S_AXI_HP0_BRESP), 2256 .m_axi_s2mm_bvalid(S_AXI_HP0_BVALID), 2257 .m_axi_s2mm_bready(S_AXI_HP0_BREADY), 2258 2259 .s2mm_prmry_reset_out_n(), 2260 .s_axis_s2mm_tdata(arm_eth0_rx_tdata), 2261 .s_axis_s2mm_tkeep(arm_eth0_rx_tkeep), 2262 .s_axis_s2mm_tvalid(arm_eth0_rx_tvalid), 2263 .s_axis_s2mm_tready(arm_eth0_rx_tready), 2264 .s_axis_s2mm_tlast(arm_eth0_rx_tlast), 2265 2266 .mm2s_introut(arm_eth0_tx_irq), 2267 .s2mm_introut(arm_eth0_rx_irq), 2268 .axi_dma_tstvec() 2269 ); 2270 2271 axi_fifo_2clk #( 2272 .WIDTH(1+8+64), 2273 .SIZE(5) 2274 ) eth_tx_0_fifo_2clk_i ( 2275 .reset(clk40_rst), 2276 .i_aclk(clk40), 2277 .i_tdata({arm_eth0_tx_tlast, arm_eth0_tx_tkeep, arm_eth0_tx_tdata}), 2278 .i_tvalid(arm_eth0_tx_tvalid), 2279 .i_tready(arm_eth0_tx_tready), 2280 .o_aclk(bus_clk), 2281 .o_tdata({arm_eth0_tx_tlast_b, arm_eth0_tx_tkeep_b, arm_eth0_tx_tdata_b}), 2282 .o_tvalid(arm_eth0_tx_tvalid_b), 2283 .o_tready(arm_eth0_tx_tready_b) 2284 ); 2285 2286 axi_fifo_2clk #( 2287 .WIDTH(1+8+64), 2288 .SIZE(5) 2289 ) eth_rx_0_fifo_2clk_i ( 2290 .reset(bus_rst), 2291 .i_aclk(bus_clk), 2292 .i_tdata({arm_eth0_rx_tlast_b, arm_eth0_rx_tkeep_b, arm_eth0_rx_tdata_b}), 2293 .i_tvalid(arm_eth0_rx_tvalid_b), 2294 .i_tready(arm_eth0_rx_tready_b), 2295 .o_aclk(clk40), 2296 .o_tdata({arm_eth0_rx_tlast, arm_eth0_rx_tkeep, arm_eth0_rx_tdata}), 2297 .o_tvalid(arm_eth0_rx_tvalid), 2298 .o_tready(arm_eth0_rx_tready) 2299 ); 2300 2301`endif 2302 2303 ///////////////////////////////////////////////////////////////////// 2304 // 2305 // Ethernet DMA 1 2306 // 2307 ////////////////////////////////////////////////////////////////////// 2308 2309 assign IRQ_F2P[2] = arm_eth1_rx_irq; 2310 assign IRQ_F2P[3] = arm_eth1_tx_irq; 2311 2312 assign {S_AXI_HP1_AWID, S_AXI_HP1_ARID} = 12'd0; 2313 assign {S_AXI_GP1_AWID, S_AXI_GP1_ARID} = 10'd0; 2314 2315`ifdef NO_ETH_DMA_1 2316 //If inst Aurora, tie off each axi/axi-lite interface 2317 axi_dummy #(.DEC_ERR(1'b0)) inst_axi_dummy_sfp1_eth_dma 2318 ( 2319 .s_axi_aclk(bus_clk), 2320 .s_axi_areset(bus_rst), 2321 2322 .s_axi_awaddr(M_AXI_ETH_DMA1_AWADDR), 2323 .s_axi_awvalid(M_AXI_ETH_DMA1_AWVALID), 2324 .s_axi_awready(M_AXI_ETH_DMA1_AWREADY), 2325 2326 .s_axi_wdata(M_AXI_ETH_DMA1_WDATA), 2327 .s_axi_wvalid(M_AXI_ETH_DMA1_WVALID), 2328 .s_axi_wready(M_AXI_ETH_DMA1_WREADY), 2329 2330 .s_axi_bresp(M_AXI_ETH_DMA1_BRESP), 2331 .s_axi_bvalid(M_AXI_ETH_DMA1_BVALID), 2332 .s_axi_bready(M_AXI_ETH_DMA1_BREADY), 2333 2334 .s_axi_araddr(M_AXI_ETH_DMA1_ARADDR), 2335 .s_axi_arvalid(M_AXI_ETH_DMA1_ARVALID), 2336 .s_axi_arready(M_AXI_ETH_DMA1_ARREADY), 2337 2338 .s_axi_rdata(M_AXI_ETH_DMA1_RDATA), 2339 .s_axi_rresp(M_AXI_ETH_DMA1_RRESP), 2340 .s_axi_rvalid(M_AXI_ETH_DMA1_RVALID), 2341 .s_axi_rready(M_AXI_ETH_DMA1_RREADY) 2342 2343 ); 2344 //S_AXI_GP0 outputs from axi_eth_dma, so needs some sort of controller/tie off 2345 assign S_AXI_GP1_AWADDR = 32'h0; 2346 assign S_AXI_GP1_AWLEN = 8'h0; 2347 assign S_AXI_GP1_AWSIZE = 4'h0; 2348 assign S_AXI_GP1_AWBURST = 3'h0; 2349 assign S_AXI_GP1_AWPROT = 3'h0; 2350 assign S_AXI_GP1_AWCACHE = 4'h0; 2351 assign S_AXI_GP1_AWVALID = 1'b0; 2352 //S_AXI_GP1_AWREADY output from PS 2353 assign S_AXI_GP1_WDATA = 32'h0; 2354 assign S_AXI_GP1_WSTRB = 4'h0; 2355 assign S_AXI_GP1_WLAST = 1'b0; 2356 assign S_AXI_GP1_WVALID = 1'b0; 2357 //S_AXI_GP1_WREADY output from PS 2358 //S_AXI_GP1_BRESP 2359 //S_AXI_GP1_BVALID 2360 assign S_AXI_GP1_BREADY = 1'b1; 2361 assign S_AXI_GP1_ARADDR = 32'h0; 2362 assign S_AXI_GP1_ARLEN = 8'h0; 2363 assign S_AXI_GP1_ARSIZE = 3'h0; 2364 assign S_AXI_GP1_ARBURST = 2'h0; 2365 assign S_AXI_GP1_ARPROT = 3'h0; 2366 assign S_AXI_GP1_ARCACHE = 4'h0; 2367 assign S_AXI_GP1_ARVALID = 1'b0; 2368 //S_AXI_GP1_ARREADY 2369 //S_AXI_GP1_RDATA 2370 //S_AXI_GP1_RRESP 2371 //S_AXI_GP1_RLAST 2372 //S_AXI_GP1_RVALID 2373 assign S_AXI_GP1_RREADY = 1'b1; 2374 2375 //S_AXI_HP0 from axi_eth_dma 2376 assign S_AXI_HP1_ARADDR = 32'h0; 2377 assign S_AXI_HP1_ARLEN = 8'h0; 2378 assign S_AXI_HP1_ARSIZE = 3'h0; 2379 assign S_AXI_HP1_ARBURST = 2'h0; 2380 assign S_AXI_HP1_ARPROT = 3'h0; 2381 assign S_AXI_HP1_ARCACHE = 4'h0; 2382 assign S_AXI_HP1_ARVALID = 1'b0; 2383 //S_AXI_HP1_ARREADY 2384 //S_AXI_HP1_RDATA 2385 //S_AXI_HP1_RRESP 2386 //S_AXI_HP1_RLAST 2387 //S_AXI_HP1_RVALID 2388 assign S_AXI_HP1_RREADY = 1'b1; 2389 assign S_AXI_HP1_AWADDR = 32'h0; 2390 assign S_AXI_HP1_AWLEN = 8'h0; 2391 assign S_AXI_HP1_AWSIZE = 3'h0; 2392 assign S_AXI_HP1_AWBURST = 2'h0; 2393 assign S_AXI_HP1_AWPROT = 3'h0; 2394 assign S_AXI_HP1_AWCACHE = 4'h0; 2395 assign S_AXI_HP1_AWVALID = 1'b0; 2396 //S_AXI_HP1_AWREADY 2397 assign S_AXI_HP1_WDATA = 64'h0; 2398 assign S_AXI_HP1_WSTRB = 8'h0; 2399 assign S_AXI_HP1_WLAST = 1'b0; 2400 assign S_AXI_HP1_WVALID = 1'b0; 2401 //S_AXI_HP1_WREADY 2402 //S_AXI_HP1_BRESP 2403 //S_AXI_HP1_BVALID 2404 assign S_AXI_HP1_BREADY = 1'b1; 2405 2406`else 2407 2408 axi_eth_dma inst_axi_eth_dma1 ( 2409 .s_axi_lite_aclk(clk40), 2410 .m_axi_sg_aclk(clk40), 2411 .m_axi_mm2s_aclk(clk40), 2412 .m_axi_s2mm_aclk(clk40), 2413 .axi_resetn(clk40_rstn), 2414 2415 .s_axi_lite_awaddr(M_AXI_ETH_DMA1_AWADDR), 2416 .s_axi_lite_awvalid(M_AXI_ETH_DMA1_AWVALID), 2417 .s_axi_lite_awready(M_AXI_ETH_DMA1_AWREADY), 2418 2419 .s_axi_lite_wdata(M_AXI_ETH_DMA1_WDATA), 2420 .s_axi_lite_wvalid(M_AXI_ETH_DMA1_WVALID), 2421 .s_axi_lite_wready(M_AXI_ETH_DMA1_WREADY), 2422 2423 .s_axi_lite_bresp(M_AXI_ETH_DMA1_BRESP), 2424 .s_axi_lite_bvalid(M_AXI_ETH_DMA1_BVALID), 2425 .s_axi_lite_bready(M_AXI_ETH_DMA1_BREADY), 2426 2427 .s_axi_lite_araddr(M_AXI_ETH_DMA1_ARADDR), 2428 .s_axi_lite_arvalid(M_AXI_ETH_DMA1_ARVALID), 2429 .s_axi_lite_arready(M_AXI_ETH_DMA1_ARREADY), 2430 2431 .s_axi_lite_rdata(M_AXI_ETH_DMA1_RDATA), 2432 .s_axi_lite_rresp(M_AXI_ETH_DMA1_RRESP), 2433 .s_axi_lite_rvalid(M_AXI_ETH_DMA1_RVALID), 2434 .s_axi_lite_rready(M_AXI_ETH_DMA1_RREADY), 2435 2436 .m_axi_sg_awaddr(S_AXI_GP1_AWADDR), 2437 .m_axi_sg_awlen(S_AXI_GP1_AWLEN), 2438 .m_axi_sg_awsize(S_AXI_GP1_AWSIZE), 2439 .m_axi_sg_awburst(S_AXI_GP1_AWBURST), 2440 .m_axi_sg_awprot(S_AXI_GP1_AWPROT), 2441 .m_axi_sg_awcache(S_AXI_GP1_AWCACHE), 2442 .m_axi_sg_awvalid(S_AXI_GP1_AWVALID), 2443 .m_axi_sg_awready(S_AXI_GP1_AWREADY), 2444 .m_axi_sg_wdata(S_AXI_GP1_WDATA), 2445 .m_axi_sg_wstrb(S_AXI_GP1_WSTRB), 2446 .m_axi_sg_wlast(S_AXI_GP1_WLAST), 2447 .m_axi_sg_wvalid(S_AXI_GP1_WVALID), 2448 .m_axi_sg_wready(S_AXI_GP1_WREADY), 2449 .m_axi_sg_bresp(S_AXI_GP1_BRESP), 2450 .m_axi_sg_bvalid(S_AXI_GP1_BVALID), 2451 .m_axi_sg_bready(S_AXI_GP1_BREADY), 2452 .m_axi_sg_araddr(S_AXI_GP1_ARADDR), 2453 .m_axi_sg_arlen(S_AXI_GP1_ARLEN), 2454 .m_axi_sg_arsize(S_AXI_GP1_ARSIZE), 2455 .m_axi_sg_arburst(S_AXI_GP1_ARBURST), 2456 .m_axi_sg_arprot(S_AXI_GP1_ARPROT), 2457 .m_axi_sg_arcache(S_AXI_GP1_ARCACHE), 2458 .m_axi_sg_arvalid(S_AXI_GP1_ARVALID), 2459 .m_axi_sg_arready(S_AXI_GP1_ARREADY), 2460 .m_axi_sg_rdata(S_AXI_GP1_RDATA), 2461 .m_axi_sg_rresp(S_AXI_GP1_RRESP), 2462 .m_axi_sg_rlast(S_AXI_GP1_RLAST), 2463 .m_axi_sg_rvalid(S_AXI_GP1_RVALID), 2464 .m_axi_sg_rready(S_AXI_GP1_RREADY), 2465 2466 .m_axi_mm2s_araddr(S_AXI_HP1_ARADDR), 2467 .m_axi_mm2s_arlen(S_AXI_HP1_ARLEN), 2468 .m_axi_mm2s_arsize(S_AXI_HP1_ARSIZE), 2469 .m_axi_mm2s_arburst(S_AXI_HP1_ARBURST), 2470 .m_axi_mm2s_arprot(S_AXI_HP1_ARPROT), 2471 .m_axi_mm2s_arcache(S_AXI_HP1_ARCACHE), 2472 .m_axi_mm2s_arvalid(S_AXI_HP1_ARVALID), 2473 .m_axi_mm2s_arready(S_AXI_HP1_ARREADY), 2474 .m_axi_mm2s_rdata(S_AXI_HP1_RDATA), 2475 .m_axi_mm2s_rresp(S_AXI_HP1_RRESP), 2476 .m_axi_mm2s_rlast(S_AXI_HP1_RLAST), 2477 .m_axi_mm2s_rvalid(S_AXI_HP1_RVALID), 2478 .m_axi_mm2s_rready(S_AXI_HP1_RREADY), 2479 2480 .mm2s_prmry_reset_out_n(), 2481 .m_axis_mm2s_tdata(arm_eth1_tx_tdata), 2482 .m_axis_mm2s_tkeep(arm_eth1_tx_tkeep), 2483 .m_axis_mm2s_tvalid(arm_eth1_tx_tvalid), 2484 .m_axis_mm2s_tready(arm_eth1_tx_tready), 2485 .m_axis_mm2s_tlast(arm_eth1_tx_tlast), 2486 2487 .m_axi_s2mm_awaddr(S_AXI_HP1_AWADDR), 2488 .m_axi_s2mm_awlen(S_AXI_HP1_AWLEN), 2489 .m_axi_s2mm_awsize(S_AXI_HP1_AWSIZE), 2490 .m_axi_s2mm_awburst(S_AXI_HP1_AWBURST), 2491 .m_axi_s2mm_awprot(S_AXI_HP1_AWPROT), 2492 .m_axi_s2mm_awcache(S_AXI_HP1_AWCACHE), 2493 .m_axi_s2mm_awvalid(S_AXI_HP1_AWVALID), 2494 .m_axi_s2mm_awready(S_AXI_HP1_AWREADY), 2495 .m_axi_s2mm_wdata(S_AXI_HP1_WDATA), 2496 .m_axi_s2mm_wstrb(S_AXI_HP1_WSTRB), 2497 .m_axi_s2mm_wlast(S_AXI_HP1_WLAST), 2498 .m_axi_s2mm_wvalid(S_AXI_HP1_WVALID), 2499 .m_axi_s2mm_wready(S_AXI_HP1_WREADY), 2500 .m_axi_s2mm_bresp(S_AXI_HP1_BRESP), 2501 .m_axi_s2mm_bvalid(S_AXI_HP1_BVALID), 2502 .m_axi_s2mm_bready(S_AXI_HP1_BREADY), 2503 2504 .s2mm_prmry_reset_out_n(), 2505 .s_axis_s2mm_tdata(arm_eth1_rx_tdata), 2506 .s_axis_s2mm_tkeep(arm_eth1_rx_tkeep), 2507 .s_axis_s2mm_tvalid(arm_eth1_rx_tvalid), 2508 .s_axis_s2mm_tready(arm_eth1_rx_tready), 2509 .s_axis_s2mm_tlast(arm_eth1_rx_tlast), 2510 2511 .mm2s_introut(arm_eth1_tx_irq), 2512 .s2mm_introut(arm_eth1_rx_irq), 2513 .axi_dma_tstvec() 2514 ); 2515 2516 axi_fifo_2clk #( 2517 .WIDTH(1+8+64), 2518 .SIZE(5) 2519 ) eth_tx_1_fifo_2clk_i ( 2520 .reset(clk40_rst), 2521 .i_aclk(clk40), 2522 .i_tdata({arm_eth1_tx_tlast, arm_eth1_tx_tkeep, arm_eth1_tx_tdata}), 2523 .i_tvalid(arm_eth1_tx_tvalid), 2524 .i_tready(arm_eth1_tx_tready), 2525 .o_aclk(bus_clk), 2526 .o_tdata({arm_eth1_tx_tlast_b, arm_eth1_tx_tkeep_b, arm_eth1_tx_tdata_b}), 2527 .o_tvalid(arm_eth1_tx_tvalid_b), 2528 .o_tready(arm_eth1_tx_tready_b) 2529 ); 2530 2531 axi_fifo_2clk #( 2532 .WIDTH(1+8+64), 2533 .SIZE(5) 2534 ) eth_rx_1_fifo_2clk_i ( 2535 .reset(bus_rst), 2536 .i_aclk(bus_clk), 2537 .i_tdata({arm_eth1_rx_tlast_b, arm_eth1_rx_tkeep_b, arm_eth1_rx_tdata_b}), 2538 .i_tvalid(arm_eth1_rx_tvalid_b), 2539 .i_tready(arm_eth1_rx_tready_b), 2540 .o_aclk(clk40), 2541 .o_tdata({arm_eth1_rx_tlast, arm_eth1_rx_tkeep, arm_eth1_rx_tdata}), 2542 .o_tvalid(arm_eth1_rx_tvalid), 2543 .o_tready(arm_eth1_rx_tready) 2544 ); 2545`endif 2546 2547 ///////////////////////////////////////////////////////////////////// 2548 // 2549 // Internal Ethernet Interface 2550 // 2551 ////////////////////////////////////////////////////////////////////// 2552 eth_internal #( 2553 .DWIDTH(REG_DWIDTH), 2554 .AWIDTH(REG_AWIDTH), 2555 .PORTNUM(8'd1) 2556 ) eth_internal_i ( 2557 // Resets 2558 .bus_rst (bus_rst), 2559 // Clocks 2560 .bus_clk (bus_clk), 2561 2562 //Axi-lite 2563 .s_axi_aclk (clk40), 2564 .s_axi_aresetn (clk40_rstn), 2565 .s_axi_awaddr (m_axi_eth_internal_awaddr), 2566 .s_axi_awvalid (m_axi_eth_internal_awvalid), 2567 .s_axi_awready (m_axi_eth_internal_awready), 2568 2569 .s_axi_wdata (m_axi_eth_internal_wdata), 2570 .s_axi_wstrb (m_axi_eth_internal_wstrb), 2571 .s_axi_wvalid (m_axi_eth_internal_wvalid), 2572 .s_axi_wready (m_axi_eth_internal_wready), 2573 2574 .s_axi_bresp (m_axi_eth_internal_bresp), 2575 .s_axi_bvalid (m_axi_eth_internal_bvalid), 2576 .s_axi_bready (m_axi_eth_internal_bready), 2577 2578 .s_axi_araddr (m_axi_eth_internal_araddr), 2579 .s_axi_arvalid (m_axi_eth_internal_arvalid), 2580 .s_axi_arready (m_axi_eth_internal_arready), 2581 2582 .s_axi_rdata (m_axi_eth_internal_rdata), 2583 .s_axi_rresp (m_axi_eth_internal_rresp), 2584 .s_axi_rvalid (m_axi_eth_internal_rvalid), 2585 .s_axi_rready (m_axi_eth_internal_rready), 2586 2587 // Host-Ethernet DMA interface 2588 .e2h_tdata (e2h_tdata), 2589 .e2h_tkeep (e2h_tkeep), 2590 .e2h_tlast (e2h_tlast), 2591 .e2h_tvalid (e2h_tvalid), 2592 .e2h_tready (e2h_tready), 2593 2594 .h2e_tdata (h2e_tdata), 2595 .h2e_tkeep (h2e_tkeep), 2596 .h2e_tlast (h2e_tlast), 2597 .h2e_tvalid (h2e_tvalid), 2598 .h2e_tready (h2e_tready), 2599 2600 // Vita router interface 2601 .e2v_tdata (m_axis_dma_tdata), 2602 .e2v_tlast (m_axis_dma_tlast), 2603 .e2v_tvalid (m_axis_dma_tvalid), 2604 .e2v_tready (m_axis_dma_tready), 2605 2606 .v2e_tdata (s_axis_dma_tdata), 2607 .v2e_tlast (s_axis_dma_tlast), 2608 .v2e_tvalid (s_axis_dma_tvalid), 2609 .v2e_tready (s_axis_dma_tready), 2610 2611 // MISC 2612 .port_info (), 2613 .device_id (device_id), 2614 2615 .link_up (), 2616 .activity () 2617 2618 ); 2619 2620 2621 ///////////////////////////////////////////////////////////////////// 2622 // 2623 // Processing System 2624 // 2625 ////////////////////////////////////////////////////////////////////// 2626 2627 wire spi0_sclk; 2628 wire spi0_mosi; 2629 wire spi0_miso; 2630 wire spi0_ss0; 2631 wire spi0_ss1; 2632 wire spi0_ss2; 2633 wire spi1_sclk; 2634 wire spi1_mosi; 2635 wire spi1_miso; 2636 wire spi1_ss0; 2637 wire spi1_ss1; 2638 wire spi1_ss2; 2639 2640 assign DBA_MODULE_PWR_ENABLE = ps_gpio_out[8]; 2641 assign DBA_RF_PWR_ENABLE = ps_gpio_out[9]; 2642 assign DBB_MODULE_PWR_ENABLE = ps_gpio_out[10]; 2643 assign DBB_RF_PWR_ENABLE = ps_gpio_out[11]; 2644 assign ps_gpio_in[8] = DBA_MODULE_PWR_ENABLE; 2645 assign ps_gpio_in[9] = DBA_RF_PWR_ENABLE; 2646 assign ps_gpio_in[10] = DBB_MODULE_PWR_ENABLE; 2647 assign ps_gpio_in[11] = DBB_RF_PWR_ENABLE; 2648 2649 // Processing System 2650 n310_ps_bd inst_n310_ps ( 2651 .SPI0_SCLK_I(1'b0), 2652 .SPI0_SCLK_O(spi0_sclk), 2653 .SPI0_SCLK_T(), 2654 .SPI0_MOSI_I(1'b0), 2655 .SPI0_MOSI_O(spi0_mosi), 2656 .SPI0_MOSI_T(), 2657 .SPI0_MISO_I(spi0_miso), 2658 .SPI0_MISO_O(), 2659 .SPI0_MISO_T(), 2660 .SPI0_SS_I(1'b1), 2661 .SPI0_SS_O(spi0_ss0), 2662 .SPI0_SS1_O(spi0_ss1), 2663 .SPI0_SS2_O(spi0_ss2), 2664 .SPI0_SS_T(), 2665 2666 .SPI1_SCLK_I(1'b0), 2667 .SPI1_SCLK_O(spi1_sclk), 2668 .SPI1_SCLK_T(), 2669 .SPI1_MOSI_I(1'b0), 2670 .SPI1_MOSI_O(spi1_mosi), 2671 .SPI1_MOSI_T(), 2672 .SPI1_MISO_I(spi1_miso), 2673 .SPI1_MISO_O(), 2674 .SPI1_MISO_T(), 2675 .SPI1_SS_I(1'b1), 2676 .SPI1_SS_O(spi1_ss0), 2677 .SPI1_SS1_O(spi1_ss1), 2678 .SPI1_SS2_O(spi1_ss2), 2679 .SPI1_SS_T(), 2680 2681 .bus_clk(bus_clk), 2682 .bus_rstn(~bus_rst), 2683 .clk40(clk40), 2684 .clk40_rstn(clk40_rstn), 2685 2686 .M_AXI_ETH_DMA0_araddr(M_AXI_ETH_DMA0_ARADDR), 2687 .M_AXI_ETH_DMA0_arprot(), 2688 .M_AXI_ETH_DMA0_arready(M_AXI_ETH_DMA0_ARREADY), 2689 .M_AXI_ETH_DMA0_arvalid(M_AXI_ETH_DMA0_ARVALID), 2690 2691 .M_AXI_ETH_DMA0_awaddr(M_AXI_ETH_DMA0_AWADDR), 2692 .M_AXI_ETH_DMA0_awprot(), 2693 .M_AXI_ETH_DMA0_awready(M_AXI_ETH_DMA0_AWREADY), 2694 .M_AXI_ETH_DMA0_awvalid(M_AXI_ETH_DMA0_AWVALID), 2695 2696 .M_AXI_ETH_DMA0_wdata(M_AXI_ETH_DMA0_WDATA), 2697 .M_AXI_ETH_DMA0_wready(M_AXI_ETH_DMA0_WREADY), 2698 .M_AXI_ETH_DMA0_wstrb(M_AXI_ETH_DMA0_WSTRB), 2699 .M_AXI_ETH_DMA0_wvalid(M_AXI_ETH_DMA0_WVALID), 2700 2701 .M_AXI_ETH_DMA0_rdata(M_AXI_ETH_DMA0_RDATA), 2702 .M_AXI_ETH_DMA0_rready(M_AXI_ETH_DMA0_RREADY), 2703 .M_AXI_ETH_DMA0_rresp(M_AXI_ETH_DMA0_RRESP), 2704 .M_AXI_ETH_DMA0_rvalid(M_AXI_ETH_DMA0_RVALID), 2705 2706 .M_AXI_ETH_DMA0_bready(M_AXI_ETH_DMA0_BREADY), 2707 .M_AXI_ETH_DMA0_bresp(M_AXI_ETH_DMA0_BRESP), 2708 .M_AXI_ETH_DMA0_bvalid(M_AXI_ETH_DMA0_BVALID), 2709 2710 .M_AXI_ETH_DMA1_araddr(M_AXI_ETH_DMA1_ARADDR), 2711 .M_AXI_ETH_DMA1_arprot(), 2712 .M_AXI_ETH_DMA1_arready(M_AXI_ETH_DMA1_ARREADY), 2713 .M_AXI_ETH_DMA1_arvalid(M_AXI_ETH_DMA1_ARVALID), 2714 2715 .M_AXI_ETH_DMA1_awaddr(M_AXI_ETH_DMA1_AWADDR), 2716 .M_AXI_ETH_DMA1_awprot(), 2717 .M_AXI_ETH_DMA1_awready(M_AXI_ETH_DMA1_AWREADY), 2718 .M_AXI_ETH_DMA1_awvalid(M_AXI_ETH_DMA1_AWVALID), 2719 2720 .M_AXI_ETH_DMA1_bready(M_AXI_ETH_DMA1_BREADY), 2721 .M_AXI_ETH_DMA1_bresp(M_AXI_ETH_DMA1_BRESP), 2722 .M_AXI_ETH_DMA1_bvalid(M_AXI_ETH_DMA1_BVALID), 2723 2724 .M_AXI_ETH_DMA1_rdata(M_AXI_ETH_DMA1_RDATA), 2725 .M_AXI_ETH_DMA1_rready(M_AXI_ETH_DMA1_RREADY), 2726 .M_AXI_ETH_DMA1_rresp(M_AXI_ETH_DMA1_RRESP), 2727 .M_AXI_ETH_DMA1_rvalid(M_AXI_ETH_DMA1_RVALID), 2728 2729 .M_AXI_ETH_DMA1_wdata(M_AXI_ETH_DMA1_WDATA), 2730 .M_AXI_ETH_DMA1_wready(M_AXI_ETH_DMA1_WREADY), 2731 .M_AXI_ETH_DMA1_wstrb(M_AXI_ETH_DMA1_WSTRB), 2732 .M_AXI_ETH_DMA1_wvalid(M_AXI_ETH_DMA1_WVALID), 2733 2734 .m_axi_eth_internal_araddr(m_axi_eth_internal_araddr), 2735 .m_axi_eth_internal_arprot(), 2736 .m_axi_eth_internal_arready(m_axi_eth_internal_arready), 2737 .m_axi_eth_internal_arvalid(m_axi_eth_internal_arvalid), 2738 .m_axi_eth_internal_awaddr(m_axi_eth_internal_awaddr), 2739 .m_axi_eth_internal_awprot(), 2740 .m_axi_eth_internal_awready(m_axi_eth_internal_awready), 2741 .m_axi_eth_internal_awvalid(m_axi_eth_internal_awvalid), 2742 .m_axi_eth_internal_bready(m_axi_eth_internal_bready), 2743 .m_axi_eth_internal_bresp(m_axi_eth_internal_bresp), 2744 .m_axi_eth_internal_bvalid(m_axi_eth_internal_bvalid), 2745 .m_axi_eth_internal_rdata(m_axi_eth_internal_rdata), 2746 .m_axi_eth_internal_rready(m_axi_eth_internal_rready), 2747 .m_axi_eth_internal_rresp(m_axi_eth_internal_rresp), 2748 .m_axi_eth_internal_rvalid(m_axi_eth_internal_rvalid), 2749 .m_axi_eth_internal_wdata(m_axi_eth_internal_wdata), 2750 .m_axi_eth_internal_wready(m_axi_eth_internal_wready), 2751 .m_axi_eth_internal_wstrb(m_axi_eth_internal_wstrb), 2752 .m_axi_eth_internal_wvalid(m_axi_eth_internal_wvalid), 2753 2754 .M_AXI_JESD0_araddr(M_AXI_JESD0_ARADDR), 2755 .M_AXI_JESD0_arprot(), 2756 .M_AXI_JESD0_arready(M_AXI_JESD0_ARREADY), 2757 .M_AXI_JESD0_arvalid(M_AXI_JESD0_ARVALID), 2758 2759 .M_AXI_JESD0_awaddr(M_AXI_JESD0_AWADDR), 2760 .M_AXI_JESD0_awprot(), 2761 .M_AXI_JESD0_awready(M_AXI_JESD0_AWREADY), 2762 .M_AXI_JESD0_awvalid(M_AXI_JESD0_AWVALID), 2763 2764 .M_AXI_JESD0_bready(M_AXI_JESD0_BREADY), 2765 .M_AXI_JESD0_bresp(M_AXI_JESD0_BRESP), 2766 .M_AXI_JESD0_bvalid(M_AXI_JESD0_BVALID), 2767 2768 .M_AXI_JESD0_rdata(M_AXI_JESD0_RDATA), 2769 .M_AXI_JESD0_rready(M_AXI_JESD0_RREADY), 2770 .M_AXI_JESD0_rresp(M_AXI_JESD0_RRESP), 2771 .M_AXI_JESD0_rvalid(M_AXI_JESD0_RVALID), 2772 2773 .M_AXI_JESD0_wdata(M_AXI_JESD0_WDATA), 2774 .M_AXI_JESD0_wready(M_AXI_JESD0_WREADY), 2775 .M_AXI_JESD0_wstrb(M_AXI_JESD0_WSTRB), 2776 .M_AXI_JESD0_wvalid(M_AXI_JESD0_WVALID), 2777 2778 .M_AXI_JESD1_araddr(M_AXI_JESD1_ARADDR), 2779 .M_AXI_JESD1_arprot(), 2780 .M_AXI_JESD1_arready(M_AXI_JESD1_ARREADY), 2781 .M_AXI_JESD1_arvalid(M_AXI_JESD1_ARVALID), 2782 2783 .M_AXI_JESD1_awaddr(M_AXI_JESD1_AWADDR), 2784 .M_AXI_JESD1_awprot(), 2785 .M_AXI_JESD1_awready(M_AXI_JESD1_AWREADY), 2786 .M_AXI_JESD1_awvalid(M_AXI_JESD1_AWVALID), 2787 2788 .M_AXI_JESD1_bready(M_AXI_JESD1_BREADY), 2789 .M_AXI_JESD1_bresp(M_AXI_JESD1_BRESP), 2790 .M_AXI_JESD1_bvalid(M_AXI_JESD1_BVALID), 2791 2792 .M_AXI_JESD1_rdata(M_AXI_JESD1_RDATA), 2793 .M_AXI_JESD1_rready(M_AXI_JESD1_RREADY), 2794 .M_AXI_JESD1_rresp(M_AXI_JESD1_RRESP), 2795 .M_AXI_JESD1_rvalid(M_AXI_JESD1_RVALID), 2796 2797 .M_AXI_JESD1_wdata(M_AXI_JESD1_WDATA), 2798 .M_AXI_JESD1_wready(M_AXI_JESD1_WREADY), 2799 .M_AXI_JESD1_wstrb(M_AXI_JESD1_WSTRB), 2800 .M_AXI_JESD1_wvalid(M_AXI_JESD1_WVALID), 2801 2802 .M_AXI_NET0_araddr(M_AXI_NET0_ARADDR), 2803 .M_AXI_NET0_arprot(), 2804 .M_AXI_NET0_arready(M_AXI_NET0_ARREADY), 2805 .M_AXI_NET0_arvalid(M_AXI_NET0_ARVALID), 2806 2807 .M_AXI_NET0_awaddr(M_AXI_NET0_AWADDR), 2808 .M_AXI_NET0_awprot(), 2809 .M_AXI_NET0_awready(M_AXI_NET0_AWREADY), 2810 .M_AXI_NET0_awvalid(M_AXI_NET0_AWVALID), 2811 2812 .M_AXI_NET0_bready(M_AXI_NET0_BREADY), 2813 .M_AXI_NET0_bresp(M_AXI_NET0_BRESP), 2814 .M_AXI_NET0_bvalid(M_AXI_NET0_BVALID), 2815 2816 .M_AXI_NET0_rdata(M_AXI_NET0_RDATA), 2817 .M_AXI_NET0_rready(M_AXI_NET0_RREADY), 2818 .M_AXI_NET0_rresp(M_AXI_NET0_RRESP), 2819 .M_AXI_NET0_rvalid(M_AXI_NET0_RVALID), 2820 2821 .M_AXI_NET0_wdata(M_AXI_NET0_WDATA), 2822 .M_AXI_NET0_wready(M_AXI_NET0_WREADY), 2823 .M_AXI_NET0_wstrb(M_AXI_NET0_WSTRB), 2824 .M_AXI_NET0_wvalid(M_AXI_NET0_WVALID), 2825 2826 .M_AXI_NET1_araddr(M_AXI_NET1_ARADDR), 2827 .M_AXI_NET1_arprot(), 2828 .M_AXI_NET1_arready(M_AXI_NET1_ARREADY), 2829 .M_AXI_NET1_arvalid(M_AXI_NET1_ARVALID), 2830 2831 .M_AXI_NET1_awaddr(M_AXI_NET1_AWADDR), 2832 .M_AXI_NET1_awprot(), 2833 .M_AXI_NET1_awready(M_AXI_NET1_AWREADY), 2834 .M_AXI_NET1_awvalid(M_AXI_NET1_AWVALID), 2835 2836 .M_AXI_NET1_bready(M_AXI_NET1_BREADY), 2837 .M_AXI_NET1_bresp(M_AXI_NET1_BRESP), 2838 .M_AXI_NET1_bvalid(M_AXI_NET1_BVALID), 2839 2840 .M_AXI_NET1_rdata(M_AXI_NET1_RDATA), 2841 .M_AXI_NET1_rready(M_AXI_NET1_RREADY), 2842 .M_AXI_NET1_rresp(M_AXI_NET1_RRESP), 2843 .M_AXI_NET1_rvalid(M_AXI_NET1_RVALID), 2844 2845 .M_AXI_NET1_wdata(M_AXI_NET1_WDATA), 2846 .M_AXI_NET1_wready(M_AXI_NET1_WREADY), 2847 .M_AXI_NET1_wstrb(M_AXI_NET1_WSTRB), 2848 .M_AXI_NET1_wvalid(M_AXI_NET1_WVALID), 2849 2850 .M_AXI_NET2_araddr(M_AXI_NET2_ARADDR), 2851 .M_AXI_NET2_arprot(), 2852 .M_AXI_NET2_arready(M_AXI_NET2_ARREADY), 2853 .M_AXI_NET2_arvalid(M_AXI_NET2_ARVALID), 2854 2855 .M_AXI_NET2_awaddr(M_AXI_NET2_AWADDR), 2856 .M_AXI_NET2_awprot(), 2857 .M_AXI_NET2_awready(M_AXI_NET2_AWREADY), 2858 .M_AXI_NET2_awvalid(M_AXI_NET2_AWVALID), 2859 2860 .M_AXI_NET2_bready(M_AXI_NET2_BREADY), 2861 .M_AXI_NET2_bresp(M_AXI_NET2_BRESP), 2862 .M_AXI_NET2_bvalid(M_AXI_NET2_BVALID), 2863 2864 .M_AXI_NET2_rdata(M_AXI_NET2_RDATA), 2865 .M_AXI_NET2_rready(M_AXI_NET2_RREADY), 2866 .M_AXI_NET2_rresp(M_AXI_NET2_RRESP), 2867 .M_AXI_NET2_rvalid(M_AXI_NET2_RVALID), 2868 2869 .M_AXI_NET2_wdata(M_AXI_NET2_WDATA), 2870 .M_AXI_NET2_wready(M_AXI_NET2_WREADY), 2871 .M_AXI_NET2_wstrb(M_AXI_NET2_WSTRB), 2872 .M_AXI_NET2_wvalid(M_AXI_NET2_WVALID), 2873 2874 .M_AXI_WR_CLK(m_axi_wr_clk), 2875 .M_AXI_WR_RSTn(1'b1), 2876 .M_AXI_WR_araddr(m_axi_wr_araddr), 2877 .M_AXI_WR_arready(m_axi_wr_arready), 2878 .M_AXI_WR_arvalid(m_axi_wr_arvalid), 2879 .M_AXI_WR_arprot(), 2880 .M_AXI_WR_awaddr(m_axi_wr_awaddr), 2881 .M_AXI_WR_awready(m_axi_wr_awready), 2882 .M_AXI_WR_awvalid(m_axi_wr_awvalid), 2883 .M_AXI_WR_awprot(), 2884 .M_AXI_WR_bready(m_axi_wr_bready), 2885 .M_AXI_WR_bresp(m_axi_wr_bresp), 2886 .M_AXI_WR_bvalid(m_axi_wr_bvalid), 2887 .M_AXI_WR_rdata(m_axi_wr_rdata), 2888 .M_AXI_WR_rready(m_axi_wr_rready), 2889 .M_AXI_WR_rresp(m_axi_wr_rresp), 2890 .M_AXI_WR_rvalid(m_axi_wr_rvalid), 2891 .M_AXI_WR_wdata(m_axi_wr_wdata), 2892 .M_AXI_WR_wready(m_axi_wr_wready), 2893 .M_AXI_WR_wstrb(m_axi_wr_wstrb), 2894 .M_AXI_WR_wvalid(m_axi_wr_wvalid), 2895 2896 .M_AXI_XBAR_araddr(M_AXI_XBAR_ARADDR), 2897 .M_AXI_XBAR_arprot(), 2898 .M_AXI_XBAR_arready(M_AXI_XBAR_ARREADY), 2899 .M_AXI_XBAR_arvalid(M_AXI_XBAR_ARVALID), 2900 2901 .M_AXI_XBAR_awaddr(M_AXI_XBAR_AWADDR), 2902 .M_AXI_XBAR_awprot(), 2903 .M_AXI_XBAR_awready(M_AXI_XBAR_AWREADY), 2904 .M_AXI_XBAR_awvalid(M_AXI_XBAR_AWVALID), 2905 2906 .M_AXI_XBAR_bready(M_AXI_XBAR_BREADY), 2907 .M_AXI_XBAR_bresp(M_AXI_XBAR_BRESP), 2908 .M_AXI_XBAR_bvalid(M_AXI_XBAR_BVALID), 2909 2910 .M_AXI_XBAR_rdata(M_AXI_XBAR_RDATA), 2911 .M_AXI_XBAR_rready(M_AXI_XBAR_RREADY), 2912 .M_AXI_XBAR_rresp(M_AXI_XBAR_RRESP), 2913 .M_AXI_XBAR_rvalid(M_AXI_XBAR_RVALID), 2914 2915 .M_AXI_XBAR_wdata(M_AXI_XBAR_WDATA), 2916 .M_AXI_XBAR_wready(M_AXI_XBAR_WREADY), 2917 .M_AXI_XBAR_wstrb(M_AXI_XBAR_WSTRB), 2918 .M_AXI_XBAR_wvalid(M_AXI_XBAR_WVALID), 2919 2920 .S_AXI_GP0_ACLK(clk40), 2921 .S_AXI_GP0_ARESETN(clk40_rstn), 2922 .S_AXI_GP0_araddr(S_AXI_GP0_ARADDR), 2923 .S_AXI_GP0_arburst(S_AXI_GP0_ARBURST), 2924 .S_AXI_GP0_arcache(S_AXI_GP0_ARCACHE), 2925 .S_AXI_GP0_arlen(S_AXI_GP0_ARLEN), 2926 .S_AXI_GP0_arlock(1'b0), 2927 .S_AXI_GP0_arprot(S_AXI_GP0_ARPROT), 2928 .S_AXI_GP0_arqos(4'b0000), 2929 .S_AXI_GP0_arready(S_AXI_GP0_ARREADY), 2930 .S_AXI_GP0_arregion(4'b0000), 2931 .S_AXI_GP0_arsize(S_AXI_GP0_ARSIZE), 2932 .S_AXI_GP0_arvalid(S_AXI_GP0_ARVALID), 2933 .S_AXI_GP0_awaddr(S_AXI_GP0_AWADDR), 2934 .S_AXI_GP0_awburst(S_AXI_GP0_AWBURST), 2935 .S_AXI_GP0_awcache(S_AXI_GP0_AWCACHE), 2936 .S_AXI_GP0_awlen(S_AXI_GP0_AWLEN), 2937 .S_AXI_GP0_awlock(1'b0), 2938 .S_AXI_GP0_awprot(S_AXI_GP0_AWPROT), 2939 .S_AXI_GP0_awqos(4'b0000), 2940 .S_AXI_GP0_awregion(4'b0000), 2941 .S_AXI_GP0_awready(S_AXI_GP0_AWREADY), 2942 .S_AXI_GP0_awsize(S_AXI_GP0_AWSIZE), 2943 .S_AXI_GP0_awvalid(S_AXI_GP0_AWVALID), 2944 .S_AXI_GP0_bready(S_AXI_GP0_BREADY), 2945 .S_AXI_GP0_bresp(S_AXI_GP0_BRESP), 2946 .S_AXI_GP0_bvalid(S_AXI_GP0_BVALID), 2947 .S_AXI_GP0_rdata(S_AXI_GP0_RDATA), 2948 .S_AXI_GP0_rlast(S_AXI_GP0_RLAST), 2949 .S_AXI_GP0_rready(S_AXI_GP0_RREADY), 2950 .S_AXI_GP0_rresp(S_AXI_GP0_RRESP), 2951 .S_AXI_GP0_rvalid(S_AXI_GP0_RVALID), 2952 .S_AXI_GP0_wdata(S_AXI_GP0_WDATA), 2953 .S_AXI_GP0_wlast(S_AXI_GP0_WLAST), 2954 .S_AXI_GP0_wready(S_AXI_GP0_WREADY), 2955 .S_AXI_GP0_wstrb(S_AXI_GP0_WSTRB), 2956 .S_AXI_GP0_wvalid(S_AXI_GP0_WVALID), 2957 2958 .S_AXI_GP1_ACLK(clk40), 2959 .S_AXI_GP1_ARESETN(clk40_rstn), 2960 .S_AXI_GP1_araddr(S_AXI_GP1_ARADDR), 2961 .S_AXI_GP1_arburst(S_AXI_GP1_ARBURST), 2962 .S_AXI_GP1_arcache(S_AXI_GP1_ARCACHE), 2963 .S_AXI_GP1_arid(S_AXI_GP1_ARID), 2964 .S_AXI_GP1_arlen(S_AXI_GP1_ARLEN), 2965 .S_AXI_GP1_arlock(1'b0), 2966 .S_AXI_GP1_arprot(S_AXI_GP1_ARPROT), 2967 .S_AXI_GP1_arqos(4'b000), 2968 .S_AXI_GP1_arregion(4'b0000), 2969 .S_AXI_GP1_arready(S_AXI_GP1_ARREADY), 2970 .S_AXI_GP1_arsize(S_AXI_GP1_ARSIZE), 2971 .S_AXI_GP1_arvalid(S_AXI_GP1_ARVALID), 2972 .S_AXI_GP1_awaddr(S_AXI_GP1_AWADDR), 2973 .S_AXI_GP1_awburst(S_AXI_GP1_AWBURST), 2974 .S_AXI_GP1_awcache(S_AXI_GP1_AWCACHE), 2975 .S_AXI_GP1_awid(S_AXI_GP1_AWID), 2976 .S_AXI_GP1_awlen(S_AXI_GP1_AWLEN), 2977 .S_AXI_GP1_awlock(1'b0), 2978 .S_AXI_GP1_awprot(S_AXI_GP1_AWPROT), 2979 .S_AXI_GP1_awqos(4'b0000), 2980 .S_AXI_GP1_awregion(4'b0000), 2981 .S_AXI_GP1_awready(S_AXI_GP1_AWREADY), 2982 .S_AXI_GP1_awsize(S_AXI_GP1_AWSIZE), 2983 .S_AXI_GP1_awvalid(S_AXI_GP1_AWVALID), 2984 .S_AXI_GP1_bid(), 2985 .S_AXI_GP1_bready(S_AXI_GP1_BREADY), 2986 .S_AXI_GP1_bresp(S_AXI_GP1_BRESP), 2987 .S_AXI_GP1_bvalid(S_AXI_GP1_BVALID), 2988 .S_AXI_GP1_rdata(S_AXI_GP1_RDATA), 2989 .S_AXI_GP1_rid(), 2990 .S_AXI_GP1_rlast(S_AXI_GP1_RLAST), 2991 .S_AXI_GP1_rready(S_AXI_GP1_RREADY), 2992 .S_AXI_GP1_rresp(S_AXI_GP1_RRESP), 2993 .S_AXI_GP1_rvalid(S_AXI_GP1_RVALID), 2994 .S_AXI_GP1_wdata(S_AXI_GP1_WDATA), 2995 .S_AXI_GP1_wlast(S_AXI_GP1_WLAST), 2996 .S_AXI_GP1_wready(S_AXI_GP1_WREADY), 2997 .S_AXI_GP1_wstrb(S_AXI_GP1_WSTRB), 2998 .S_AXI_GP1_wvalid(S_AXI_GP1_WVALID), 2999 3000 .S_AXI_HP0_ACLK(clk40), 3001 .S_AXI_HP0_ARESETN(clk40_rstn), 3002 .S_AXI_HP0_araddr(S_AXI_HP0_ARADDR), 3003 .S_AXI_HP0_arburst(S_AXI_HP0_ARBURST), 3004 .S_AXI_HP0_arcache(S_AXI_HP0_ARCACHE), 3005 .S_AXI_HP0_arlen(S_AXI_HP0_ARLEN), 3006 .S_AXI_HP0_arlock(1'b0), 3007 .S_AXI_HP0_arprot(S_AXI_HP0_ARPROT), 3008 .S_AXI_HP0_arqos(4'b0000), 3009 .S_AXI_HP0_arready(S_AXI_HP0_ARREADY), 3010 .S_AXI_HP0_arregion(4'b0), 3011 .S_AXI_HP0_arsize(S_AXI_HP0_ARSIZE), 3012 .S_AXI_HP0_arvalid(S_AXI_HP0_ARVALID), 3013 .S_AXI_HP0_awaddr(S_AXI_HP0_AWADDR), 3014 .S_AXI_HP0_awburst(S_AXI_HP0_AWBURST), 3015 .S_AXI_HP0_awcache(S_AXI_HP0_AWCACHE), 3016 .S_AXI_HP0_awlen(S_AXI_HP0_AWLEN), 3017 .S_AXI_HP0_awlock(1'b0), 3018 .S_AXI_HP0_awprot(S_AXI_HP0_AWPROT), 3019 .S_AXI_HP0_awqos(4'b0000), 3020 .S_AXI_HP0_awready(S_AXI_HP0_AWREADY), 3021 .S_AXI_HP0_awregion(4'b0), 3022 .S_AXI_HP0_awsize(S_AXI_HP0_AWSIZE), 3023 .S_AXI_HP0_awvalid(S_AXI_HP0_AWVALID), 3024 .S_AXI_HP0_bready(S_AXI_HP0_BREADY), 3025 .S_AXI_HP0_bresp(S_AXI_HP0_BRESP), 3026 .S_AXI_HP0_bvalid(S_AXI_HP0_BVALID), 3027 .S_AXI_HP0_rdata(S_AXI_HP0_RDATA), 3028 .S_AXI_HP0_rlast(S_AXI_HP0_RLAST), 3029 .S_AXI_HP0_rready(S_AXI_HP0_RREADY), 3030 .S_AXI_HP0_rresp(S_AXI_HP0_RRESP), 3031 .S_AXI_HP0_rvalid(S_AXI_HP0_RVALID), 3032 .S_AXI_HP0_wdata(S_AXI_HP0_WDATA), 3033 .S_AXI_HP0_wlast(S_AXI_HP0_WLAST), 3034 .S_AXI_HP0_wready(S_AXI_HP0_WREADY), 3035 .S_AXI_HP0_wstrb(S_AXI_HP0_WSTRB), 3036 .S_AXI_HP0_wvalid(S_AXI_HP0_WVALID), 3037 3038 .S_AXI_HP1_ACLK(clk40), 3039 .S_AXI_HP1_ARESETN(clk40_rstn), 3040 .S_AXI_HP1_araddr(S_AXI_HP1_ARADDR), 3041 .S_AXI_HP1_arburst(S_AXI_HP1_ARBURST), 3042 .S_AXI_HP1_arcache(S_AXI_HP1_ARCACHE), 3043 .S_AXI_HP1_arid(S_AXI_HP1_ARID), 3044 .S_AXI_HP1_arlen(S_AXI_HP1_ARLEN), 3045 .S_AXI_HP1_arlock(1'b0), 3046 .S_AXI_HP1_arprot(S_AXI_HP1_ARPROT), 3047 .S_AXI_HP1_arqos(4'b0000), 3048 .S_AXI_HP1_arready(S_AXI_HP1_ARREADY), 3049 .S_AXI_HP1_arsize(S_AXI_HP1_ARSIZE), 3050 .S_AXI_HP1_arvalid(S_AXI_HP1_ARVALID), 3051 .S_AXI_HP1_awaddr(S_AXI_HP1_AWADDR), 3052 .S_AXI_HP1_awburst(S_AXI_HP1_AWBURST), 3053 .S_AXI_HP1_awcache(S_AXI_HP1_AWCACHE), 3054 .S_AXI_HP1_awid(S_AXI_HP1_AWID), 3055 .S_AXI_HP1_awlen(S_AXI_HP1_AWLEN), 3056 .S_AXI_HP1_awlock(1'b0), 3057 .S_AXI_HP1_awprot(S_AXI_HP1_AWPROT), 3058 .S_AXI_HP1_awqos(4'b0000), 3059 .S_AXI_HP1_awready(S_AXI_HP1_AWREADY), 3060 .S_AXI_HP1_awsize(S_AXI_HP1_AWSIZE), 3061 .S_AXI_HP1_awvalid(S_AXI_HP1_AWVALID), 3062 .S_AXI_HP1_bid(), 3063 .S_AXI_HP1_bready(S_AXI_HP1_BREADY), 3064 .S_AXI_HP1_bresp(S_AXI_HP1_BRESP), 3065 .S_AXI_HP1_bvalid(S_AXI_HP1_BVALID), 3066 .S_AXI_HP1_rdata(S_AXI_HP1_RDATA), 3067 .S_AXI_HP1_rid(), 3068 .S_AXI_HP1_rlast(S_AXI_HP1_RLAST), 3069 .S_AXI_HP1_rready(S_AXI_HP1_RREADY), 3070 .S_AXI_HP1_rresp(S_AXI_HP1_RRESP), 3071 .S_AXI_HP1_rvalid(S_AXI_HP1_RVALID), 3072 .S_AXI_HP1_wdata(S_AXI_HP1_WDATA), 3073 .S_AXI_HP1_wlast(S_AXI_HP1_WLAST), 3074 .S_AXI_HP1_wready(S_AXI_HP1_WREADY), 3075 .S_AXI_HP1_wstrb(S_AXI_HP1_WSTRB), 3076 .S_AXI_HP1_wvalid(S_AXI_HP1_WVALID), 3077 3078 // ARM DMA 3079 .s_axis_dma_tdata(e2h_tdata), 3080 .s_axis_dma_tkeep(e2h_tkeep), 3081 .s_axis_dma_tlast(e2h_tlast), 3082 .s_axis_dma_tready(e2h_tready), 3083 .s_axis_dma_tvalid(e2h_tvalid), 3084 .m_axis_dma_tdata(h2e_tdata), 3085 .m_axis_dma_tkeep(h2e_tkeep), 3086 .m_axis_dma_tlast(h2e_tlast), 3087 .m_axis_dma_tready(h2e_tready), 3088 .m_axis_dma_tvalid(h2e_tvalid), 3089 3090 // Misc Interrupts, GPIO, clk 3091 .IRQ_F2P(IRQ_F2P), 3092 3093 .GPIO_0_tri_i(ps_gpio_in), 3094 .GPIO_0_tri_o(ps_gpio_out), 3095 .GPIO_0_tri_t(ps_gpio_tri), 3096 3097 .JTAG0_TCK(DBA_CPLD_JTAG_TCK), 3098 .JTAG0_TMS(DBA_CPLD_JTAG_TMS), 3099 .JTAG0_TDI(DBA_CPLD_JTAG_TDI), 3100 .JTAG0_TDO(DBA_CPLD_JTAG_TDO), 3101 3102 .JTAG1_TCK(DBB_CPLD_JTAG_TCK), 3103 .JTAG1_TMS(DBB_CPLD_JTAG_TMS), 3104 .JTAG1_TDI(DBB_CPLD_JTAG_TDI), 3105 .JTAG1_TDO(DBB_CPLD_JTAG_TDO), 3106 3107 .FCLK_CLK0(FCLK_CLK0), 3108 .FCLK_RESET0_N(FCLK_RESET0_N), 3109 .FCLK_CLK1(FCLK_CLK1), 3110 .FCLK_RESET1_N(), 3111 .FCLK_CLK2(FCLK_CLK2), 3112 .FCLK_RESET2_N(), 3113 .FCLK_CLK3(FCLK_CLK3), 3114 .FCLK_RESET3_N(), 3115 3116 .WR_UART_txd(wr_uart_rxd), // rx <-> tx 3117 .WR_UART_rxd(wr_uart_txd), // rx <-> tx 3118 3119 .qsfp_sda_i(qsfp_sda_i), 3120 .qsfp_sda_o(qsfp_sda_o), 3121 .qsfp_sda_t(qsfp_sda_t), 3122 .qsfp_scl_i(qsfp_scl_i), 3123 .qsfp_scl_o(qsfp_scl_o), 3124 .qsfp_scl_t(qsfp_scl_t), 3125 3126 .USBIND_0_port_indctl(), 3127 .USBIND_0_vbus_pwrfault(), 3128 .USBIND_0_vbus_pwrselect(), 3129 3130 // Outward connections to the pins 3131 .MIO(MIO), 3132 .DDR_cas_n(DDR_CAS_n), 3133 .DDR_cke(DDR_CKE), 3134 .DDR_ck_n(DDR_Clk_n), 3135 .DDR_ck_p(DDR_Clk), 3136 .DDR_cs_n(DDR_CS_n), 3137 .DDR_reset_n(DDR_DRSTB), 3138 .DDR_odt(DDR_ODT), 3139 .DDR_ras_n(DDR_RAS_n), 3140 .DDR_we_n(DDR_WEB), 3141 .DDR_ba(DDR_BankAddr), 3142 .DDR_addr(DDR_Addr), 3143 .DDR_VRN(DDR_VRN), 3144 .DDR_VRP(DDR_VRP), 3145 .DDR_dm(DDR_DM), 3146 .DDR_dq(DDR_DQ), 3147 .DDR_dqs_n(DDR_DQS_n), 3148 .DDR_dqs_p(DDR_DQS), 3149 .PS_SRSTB(PS_SRSTB), 3150 .PS_CLK(PS_CLK), 3151 .PS_PORB(PS_PORB) 3152 ); 3153 3154 /////////////////////////////////////////////////////////////////////////////////// 3155 // 3156 // Xilinx DDR3 Controller and PHY. 3157 // 3158 /////////////////////////////////////////////////////////////////////////////////// 3159 3160 wire ddr3_axi_clk; // 1/4 DDR external clock rate (200MHz) 3161 wire ddr3_axi_rst; // Synchronized to ddr_sys_clk 3162 wire ddr3_running; // DRAM calibration complete. 3163 wire [11:0] device_temp; 3164 3165 // Slave Interface Write Address Ports 3166 wire [3:0] ddr3_axi_awid; 3167 wire [31:0] ddr3_axi_awaddr; 3168 wire [7:0] ddr3_axi_awlen; 3169 wire [2:0] ddr3_axi_awsize; 3170 wire [1:0] ddr3_axi_awburst; 3171 wire [0:0] ddr3_axi_awlock; 3172 wire [3:0] ddr3_axi_awcache; 3173 wire [2:0] ddr3_axi_awprot; 3174 wire [3:0] ddr3_axi_awqos; 3175 wire ddr3_axi_awvalid; 3176 wire ddr3_axi_awready; 3177 // Slave Interface Write Data Ports 3178 wire [255:0] ddr3_axi_wdata; 3179 wire [31:0] ddr3_axi_wstrb; 3180 wire ddr3_axi_wlast; 3181 wire ddr3_axi_wvalid; 3182 wire ddr3_axi_wready; 3183 // Slave Interface Write Response Ports 3184 wire ddr3_axi_bready; 3185 wire [3:0] ddr3_axi_bid; 3186 wire [1:0] ddr3_axi_bresp; 3187 wire ddr3_axi_bvalid; 3188 // Slave Interface Read Address Ports 3189 wire [3:0] ddr3_axi_arid; 3190 wire [31:0] ddr3_axi_araddr; 3191 wire [7:0] ddr3_axi_arlen; 3192 wire [2:0] ddr3_axi_arsize; 3193 wire [1:0] ddr3_axi_arburst; 3194 wire [0:0] ddr3_axi_arlock; 3195 wire [3:0] ddr3_axi_arcache; 3196 wire [2:0] ddr3_axi_arprot; 3197 wire [3:0] ddr3_axi_arqos; 3198 wire ddr3_axi_arvalid; 3199 wire ddr3_axi_arready; 3200 // Slave Interface Read Data Ports 3201 wire ddr3_axi_rready; 3202 wire [3:0] ddr3_axi_rid; 3203 wire [255:0] ddr3_axi_rdata; 3204 wire [1:0] ddr3_axi_rresp; 3205 wire ddr3_axi_rlast; 3206 wire ddr3_axi_rvalid; 3207 3208 reg ddr3_axi_rst_reg_n; 3209 3210 // Copied this reset circuit from example design. 3211 always @(posedge ddr3_axi_clk) 3212 ddr3_axi_rst_reg_n <= ~ddr3_axi_rst; 3213 3214 3215 // Instantiate the DDR3 MIG core 3216 // 3217 // The top-level IP block has no parameters defined for some reason. 3218 // Most of configurable parameters are hard-coded in the mig so get 3219 // some additional knobs we pull those out into verilog headers. 3220 // 3221 // Synthesis params: ip/ddr3_32bit/ddr3_32bit_mig_parameters.vh 3222 // Simulation params: ip/ddr3_32bit/ddr3_32bit_mig_sim_parameters.vh 3223 3224 ddr3_32bit u_ddr3_32bit ( 3225 // Memory interface ports 3226 .ddr3_addr (ddr3_addr), 3227 .ddr3_ba (ddr3_ba), 3228 .ddr3_cas_n (ddr3_cas_n), 3229 .ddr3_ck_n (ddr3_ck_n), 3230 .ddr3_ck_p (ddr3_ck_p), 3231 .ddr3_cke (ddr3_cke), 3232 .ddr3_ras_n (ddr3_ras_n), 3233 .ddr3_reset_n (ddr3_reset_n), 3234 .ddr3_we_n (ddr3_we_n), 3235 .ddr3_dq (ddr3_dq), 3236 .ddr3_dqs_n (ddr3_dqs_n), 3237 .ddr3_dqs_p (ddr3_dqs_p), 3238 .init_calib_complete (ddr3_running), 3239 .device_temp_i (device_temp), 3240 3241 .ddr3_cs_n (ddr3_cs_n), 3242 .ddr3_dm (ddr3_dm), 3243 .ddr3_odt (ddr3_odt), 3244 // Application interface ports 3245 .ui_clk (ddr3_axi_clk), // 200Hz clock out 3246 .ui_clk_sync_rst (ddr3_axi_rst), // Active high Reset signal synchronised to 200 MHz. 3247 .aresetn (ddr3_axi_rst_reg_n), 3248 .app_sr_req (1'b0), 3249 .app_sr_active (), 3250 .app_ref_req (1'b0), 3251 .app_ref_ack (), 3252 .app_zq_req (1'b0), 3253 .app_zq_ack (), 3254 // Slave Interface Write Address Ports 3255 .s_axi_awid (ddr3_axi_awid), 3256 .s_axi_awaddr (ddr3_axi_awaddr), 3257 .s_axi_awlen (ddr3_axi_awlen), 3258 .s_axi_awsize (ddr3_axi_awsize), 3259 .s_axi_awburst (ddr3_axi_awburst), 3260 .s_axi_awlock (ddr3_axi_awlock), 3261 .s_axi_awcache (ddr3_axi_awcache), 3262 .s_axi_awprot (ddr3_axi_awprot), 3263 .s_axi_awqos (ddr3_axi_awqos), 3264 .s_axi_awvalid (ddr3_axi_awvalid), 3265 .s_axi_awready (ddr3_axi_awready), 3266 // Slave Interface Write Data Ports 3267 .s_axi_wdata (ddr3_axi_wdata), 3268 .s_axi_wstrb (ddr3_axi_wstrb), 3269 .s_axi_wlast (ddr3_axi_wlast), 3270 .s_axi_wvalid (ddr3_axi_wvalid), 3271 .s_axi_wready (ddr3_axi_wready), 3272 // Slave Interface Write Response Ports 3273 .s_axi_bid (ddr3_axi_bid), 3274 .s_axi_bresp (ddr3_axi_bresp), 3275 .s_axi_bvalid (ddr3_axi_bvalid), 3276 .s_axi_bready (ddr3_axi_bready), 3277 // Slave Interface Read Address Ports 3278 .s_axi_arid (ddr3_axi_arid), 3279 .s_axi_araddr (ddr3_axi_araddr), 3280 .s_axi_arlen (ddr3_axi_arlen), 3281 .s_axi_arsize (ddr3_axi_arsize), 3282 .s_axi_arburst (ddr3_axi_arburst), 3283 .s_axi_arlock (ddr3_axi_arlock), 3284 .s_axi_arcache (ddr3_axi_arcache), 3285 .s_axi_arprot (ddr3_axi_arprot), 3286 .s_axi_arqos (ddr3_axi_arqos), 3287 .s_axi_arvalid (ddr3_axi_arvalid), 3288 .s_axi_arready (ddr3_axi_arready), 3289 // Slave Interface Read Data Ports 3290 .s_axi_rid (ddr3_axi_rid), 3291 .s_axi_rdata (ddr3_axi_rdata), 3292 .s_axi_rresp (ddr3_axi_rresp), 3293 .s_axi_rlast (ddr3_axi_rlast), 3294 .s_axi_rvalid (ddr3_axi_rvalid), 3295 .s_axi_rready (ddr3_axi_rready), 3296 // System Clock Ports 3297 .sys_clk_p (sys_clk_p), 3298 .sys_clk_n (sys_clk_n), 3299 .clk_ref_i (bus_clk), 3300 3301 .sys_rst (~global_rst) // IJB. Poorly named active low. Should change RST_ACT_LOW. 3302 ); 3303 3304 // Temperature monitor module 3305 mig_7series_v4_2_tempmon #( 3306 .TEMP_MON_CONTROL("INTERNAL"), 3307 .XADC_CLK_PERIOD(5000 /* 200MHz clock period in ps */) 3308 ) tempmon_i ( 3309 .clk(bus_clk), .xadc_clk(bus_clk), .rst(bus_rst), 3310 .device_temp_i(12'd0 /* ignored */), .device_temp(device_temp) 3311 ); 3312 3313 /////////////////////////////////////////////////////// 3314 // 3315 // DB PS SPI Connections 3316 // 3317 /////////////////////////////////////////////////////// 3318 wire [NUM_CHANNELS-1:0] rx_atr; 3319 wire [NUM_CHANNELS-1:0] tx_atr; 3320 (* IOB = "true" *) reg [NUM_CHANNELS-1:0] rx_atr_reg; 3321 (* IOB = "true" *) reg [NUM_CHANNELS-1:0] tx_atr_reg; 3322 3323 // Radio GPIO control for DSA 3324 wire [16*NUM_CHANNELS-1:0] db_gpio_out; 3325 wire [16*NUM_CHANNELS-1:0] db_gpio_ddr; 3326 wire [16*NUM_CHANNELS-1:0] db_gpio_in; 3327 wire [16*NUM_CHANNELS-1:0] db_gpio_fab; 3328 3329 // DB A SPI Connections 3330 assign DBA_CPLD_PS_SPI_SCLK = spi0_sclk; 3331 assign DBA_CPLD_PS_SPI_MOSI = spi0_mosi; 3332 3333 // Assign individual chip selects from PS SPI MASTER 0. 3334 assign DBA_CPLD_PS_SPI_CS_B = spi0_ss0; 3335 assign DBA_CLKDIS_SPI_CS_B = spi0_ss1; 3336 assign DBA_PHDAC_SPI_CS_B = spi0_ss2; 3337 assign DBA_ADC_SPI_CS_B = ps_gpio_out[13]; 3338 assign DBA_DAC_SPI_CS_B = ps_gpio_out[14]; 3339 3340 // Returned data mux from the SPI interfaces. 3341 assign spi0_miso = DBA_CPLD_PS_SPI_MISO; 3342 3343 // TODO: How to control? 3344 assign DBA_ATR_RX = rx_atr_reg[0]; 3345 assign DBA_ATR_TX = tx_atr_reg[0]; 3346 assign DBA_TXRX_SW_CTRL_1 = db_gpio_out[16*0+0]; 3347 assign DBA_TXRX_SW_CTRL_2 = db_gpio_out[16*0+1]; 3348 assign DBA_LED_RX = db_gpio_out[16*0+2]; 3349 assign DBA_LED_RX2 = db_gpio_out[16*0+3]; 3350 assign DBA_LED_TX = db_gpio_out[16*0+4]; 3351 3352 // DB B SPI Connections 3353 assign DBB_CPLD_PS_SPI_SCLK = spi1_sclk; 3354 assign DBB_CPLD_PS_SPI_MOSI = spi1_mosi; 3355 3356 // Assign individual chip selects from PS SPI MASTER 1. 3357 assign DBB_CPLD_PS_SPI_CS_B = spi1_ss0; 3358 assign DBB_CLKDIS_SPI_CS_B = spi1_ss1; 3359 assign DBB_PHDAC_SPI_CS_B = spi1_ss2; 3360 assign DBB_ADC_SPI_CS_B = ps_gpio_out[15]; 3361 assign DBB_DAC_SPI_CS_B = ps_gpio_out[16]; 3362 3363 // Returned data mux from the SPI interfaces. 3364 assign spi1_miso = DBB_CPLD_PS_SPI_MISO; 3365 3366 3367 // TODO: How to control? 3368 assign DBB_ATR_RX = rx_atr_reg[1]; 3369 assign DBB_ATR_TX = tx_atr_reg[1]; 3370 assign DBB_TXRX_SW_CTRL_1 = db_gpio_out[16*1+0]; 3371 assign DBB_TXRX_SW_CTRL_2 = db_gpio_out[16*1+1]; 3372 assign DBB_LED_RX = db_gpio_out[16*1+2]; 3373 assign DBB_LED_RX2 = db_gpio_out[16*1+3]; 3374 assign DBB_LED_TX = db_gpio_out[16*1+4]; 3375 3376 3377 /////////////////////////////////////////////////////// 3378 // 3379 // N320 CORE 3380 // 3381 /////////////////////////////////////////////////////// 3382 3383 wire [CHANNEL_WIDTH-1:0] rx_db[2*NUM_CHANNELS-1:0]; 3384 wire [CHANNEL_WIDTH-1:0] tx_db[2*NUM_CHANNELS-1:0]; 3385 wire [CHANNEL_WIDTH-1:0] rx[NUM_CHANNELS-1:0]; 3386 wire [CHANNEL_WIDTH-1:0] tx[NUM_CHANNELS-1:0]; 3387 wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] rx_flat; 3388 wire [CHANNEL_WIDTH*NUM_CHANNELS-1:0] tx_flat; 3389 wire [47:0] rx_hb[NUM_CHANNELS-1:0]; 3390 wire [95:0] tx_hb[NUM_CHANNELS-1:0]; 3391 3392 wire [NUM_CHANNELS-1:0] rx_stb; 3393 wire [NUM_CHANNELS-1:0] tx_stb; 3394 3395 wire [31:0] build_datestamp; 3396 3397 /* 2:1 and 1:2 filters to bring sample rates down 3398 */ 3399 genvar i; 3400 generate for (i = 0; i < NUM_CHANNELS; i = i + 1) begin 3401 hb47_1to2 tx_1to2 ( 3402 .aresetn(!radio_rst), 3403 .aclk(radio_clk), 3404 .s_axis_data_tvalid(tx_stb[i]), 3405 .s_axis_data_tready(), 3406 .s_axis_data_tdata(tx[i]), 3407 .m_axis_data_tvalid(), 3408 .m_axis_data_tready(tx_stb[i]), 3409 .m_axis_data_tdata(tx_hb[i]) 3410 ); 3411 3412 assign tx_db[2*i] = {tx_hb[i][39:24], tx_hb[i][15:0]}; 3413 assign tx_db[2*i+1] = {tx_hb[i][87:72], tx_hb[i][63:48]}; 3414 3415 hb47_2to1 rx_2to1 ( 3416 .aresetn(!radio_rst), 3417 .aclk(radio_clk), 3418 .s_axis_data_tvalid(rx_stb[i]), 3419 .s_axis_data_tready(), 3420 .s_axis_data_tdata({rx_db[2*i+1], rx_db[2*i]}), 3421 .m_axis_data_tvalid(), 3422 .m_axis_data_tdata(rx_hb[i]) 3423 ); 3424 3425 assign rx[i] = {rx_hb[i][39:24], rx_hb[i][15:0]}; 3426 end endgenerate 3427 3428 generate 3429 for (i = 0; i < NUM_CHANNELS; i = i + 1) begin 3430 // Radio Data 3431 assign rx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH] = rx[i]; 3432 assign tx[i] = tx_flat[CHANNEL_WIDTH*i +: CHANNEL_WIDTH]; 3433 end 3434 endgenerate 3435 3436 USR_ACCESSE2 usr_access_i ( 3437 .DATA(build_datestamp), .CFGCLK(), .DATAVALID() 3438 ); 3439 3440 n3xx_core #( 3441 .REG_AWIDTH(14), 3442 .BUS_CLK_RATE(BUS_CLK_RATE), 3443 .FP_GPIO_WIDTH(FP_GPIO_WIDTH), 3444 .CHANNEL_WIDTH(CHANNEL_WIDTH), 3445 .NUM_CHANNELS_PER_RADIO(NUM_CHANNELS_PER_RADIO), 3446 .NUM_CHANNELS(NUM_CHANNELS), 3447 .NUM_DBOARDS(NUM_DBOARDS), 3448 .NUM_SPI_PER_DBOARD(4), 3449 .USE_CORRECTION(1), 3450 `ifdef USE_REPLAY 3451 .USE_REPLAY(1) 3452 `else 3453 .USE_REPLAY(0) 3454 `endif 3455 ) n3xx_core( 3456 // Clocks and resets 3457`ifdef NO_DB 3458 .radio_clk(bus_clk), 3459 .radio_rst(bus_rst), 3460`else 3461 .radio_clk(radio_clk), 3462 .radio_rst(radio_rst), 3463`endif 3464 .bus_clk(bus_clk), 3465 .bus_rst(bus_rst), 3466 .ddr3_dma_clk(ddr3_dma_clk), 3467 .clk40(clk40), 3468 3469 // Clocking and PPS Controls/Indicators 3470 .pps(pps_radioclk1x), 3471 .pps_select(pps_select), 3472 .pps_out_enb(pps_out_enb), 3473 .pps_select_sfp(pps_select_sfp), 3474 .ref_clk_reset(), 3475 .meas_clk_reset(meas_clk_reset), 3476 .ref_clk_locked(1'b1), 3477 .meas_clk_locked(meas_clk_locked), 3478 .enable_ref_clk_async(enable_ref_clk_async), 3479 3480 .s_axi_aclk(clk40), 3481 .s_axi_aresetn(clk40_rstn), 3482 // AXI4-Lite: Write address port (domain: s_axi_aclk) 3483 .s_axi_awaddr(M_AXI_XBAR_AWADDR), 3484 .s_axi_awvalid(M_AXI_XBAR_AWVALID), 3485 .s_axi_awready(M_AXI_XBAR_AWREADY), 3486 // AXI4-Lite: Write data port (domain: s_axi_aclk) 3487 .s_axi_wdata(M_AXI_XBAR_WDATA), 3488 .s_axi_wstrb(M_AXI_XBAR_WSTRB), 3489 .s_axi_wvalid(M_AXI_XBAR_WVALID), 3490 .s_axi_wready(M_AXI_XBAR_WREADY), 3491 // AXI4-Lite: Write response port (domain: s_axi_aclk) 3492 .s_axi_bresp(M_AXI_XBAR_BRESP), 3493 .s_axi_bvalid(M_AXI_XBAR_BVALID), 3494 .s_axi_bready(M_AXI_XBAR_BREADY), 3495 // AXI4-Lite: Read address port (domain: s_axi_aclk) 3496 .s_axi_araddr(M_AXI_XBAR_ARADDR), 3497 .s_axi_arvalid(M_AXI_XBAR_ARVALID), 3498 .s_axi_arready(M_AXI_XBAR_ARREADY), 3499 // AXI4-Lite: Read data port (domain: s_axi_aclk) 3500 .s_axi_rdata(M_AXI_XBAR_RDATA), 3501 .s_axi_rresp(M_AXI_XBAR_RRESP), 3502 .s_axi_rvalid(M_AXI_XBAR_RVALID), 3503 .s_axi_rready(M_AXI_XBAR_RREADY), 3504 // ps gpio source 3505 .ps_gpio_tri(ps_gpio_tri[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), 3506 .ps_gpio_out(ps_gpio_out[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), 3507 .ps_gpio_in(ps_gpio_in[FP_GPIO_WIDTH+FP_GPIO_OFFSET-1:FP_GPIO_OFFSET]), 3508 // FP_GPIO 3509 .fp_gpio_inout(FPGA_GPIO), 3510 // Radio ATR 3511 .rx_atr(rx_atr), 3512 .tx_atr(tx_atr), 3513 // Radio GPIO DSA 3514 .db_gpio_out_flat(db_gpio_out), 3515 .db_gpio_in_flat(db_gpio_in), 3516 .db_gpio_ddr_flat(db_gpio_ddr), 3517 .db_gpio_fab_flat(db_gpio_fab), 3518 // Radio Strobes 3519 .rx_stb(rx_stb), 3520 .tx_stb(tx_stb), 3521 // Radio Data 3522 .rx(rx_flat), 3523 .tx(tx_flat), 3524 //cpld rx_lo tx_lo spi 3525 .sclk_flat({DBB_CPLD_PL_SPI_SCLK, 3526 DBA_CPLD_PL_SPI_SCLK}), 3527 .sen_flat({DBB_CPLD_PL_SPI_CS_B,DBB_LODIS_SPI_CS_B,DBB_RXLO_SPI_CS_B,DBB_TXLO_SPI_CS_B, 3528 DBA_CPLD_PL_SPI_CS_B,DBA_LODIS_SPI_CS_B,DBA_RXLO_SPI_CS_B,DBA_TXLO_SPI_CS_B}), 3529 .mosi_flat({DBB_CPLD_PL_SPI_MOSI, 3530 DBA_CPLD_PL_SPI_MOSI}), 3531 .miso_flat({DBB_CPLD_PL_SPI_MISO, 3532 DBA_CPLD_PL_SPI_MISO}), 3533 // DRAM signals. 3534 .ddr3_axi_clk (ddr3_axi_clk), 3535 .ddr3_axi_rst (ddr3_axi_rst), 3536 .ddr3_running (ddr3_running), 3537 // Slave Interface Write Address Ports 3538 .ddr3_axi_awid (ddr3_axi_awid), 3539 .ddr3_axi_awaddr (ddr3_axi_awaddr), 3540 .ddr3_axi_awlen (ddr3_axi_awlen), 3541 .ddr3_axi_awsize (ddr3_axi_awsize), 3542 .ddr3_axi_awburst (ddr3_axi_awburst), 3543 .ddr3_axi_awlock (ddr3_axi_awlock), 3544 .ddr3_axi_awcache (ddr3_axi_awcache), 3545 .ddr3_axi_awprot (ddr3_axi_awprot), 3546 .ddr3_axi_awqos (ddr3_axi_awqos), 3547 .ddr3_axi_awvalid (ddr3_axi_awvalid), 3548 .ddr3_axi_awready (ddr3_axi_awready), 3549 // Slave Interface Write Data Ports 3550 .ddr3_axi_wdata (ddr3_axi_wdata), 3551 .ddr3_axi_wstrb (ddr3_axi_wstrb), 3552 .ddr3_axi_wlast (ddr3_axi_wlast), 3553 .ddr3_axi_wvalid (ddr3_axi_wvalid), 3554 .ddr3_axi_wready (ddr3_axi_wready), 3555 // Slave Interface Write Response Ports 3556 .ddr3_axi_bid (ddr3_axi_bid), 3557 .ddr3_axi_bresp (ddr3_axi_bresp), 3558 .ddr3_axi_bvalid (ddr3_axi_bvalid), 3559 .ddr3_axi_bready (ddr3_axi_bready), 3560 // Slave Interface Read Address Ports 3561 .ddr3_axi_arid (ddr3_axi_arid), 3562 .ddr3_axi_araddr (ddr3_axi_araddr), 3563 .ddr3_axi_arlen (ddr3_axi_arlen), 3564 .ddr3_axi_arsize (ddr3_axi_arsize), 3565 .ddr3_axi_arburst (ddr3_axi_arburst), 3566 .ddr3_axi_arlock (ddr3_axi_arlock), 3567 .ddr3_axi_arcache (ddr3_axi_arcache), 3568 .ddr3_axi_arprot (ddr3_axi_arprot), 3569 .ddr3_axi_arqos (ddr3_axi_arqos), 3570 .ddr3_axi_arvalid (ddr3_axi_arvalid), 3571 .ddr3_axi_arready (ddr3_axi_arready), 3572 // Slave Interface Read Data Ports 3573 .ddr3_axi_rid (ddr3_axi_rid), 3574 .ddr3_axi_rdata (ddr3_axi_rdata), 3575 .ddr3_axi_rresp (ddr3_axi_rresp), 3576 .ddr3_axi_rlast (ddr3_axi_rlast), 3577 .ddr3_axi_rvalid (ddr3_axi_rvalid), 3578 .ddr3_axi_rready (ddr3_axi_rready), 3579 3580 // Internal Ethernet DMA to PS 3581 .m_dma_tdata(s_axis_dma_tdata), 3582 .m_dma_tlast(s_axis_dma_tlast), 3583 .m_dma_tready(s_axis_dma_tready), 3584 .m_dma_tvalid(s_axis_dma_tvalid), 3585 3586 .s_dma_tdata(m_axis_dma_tdata), 3587 .s_dma_tlast(m_axis_dma_tlast), 3588 .s_dma_tready(m_axis_dma_tready), 3589 .s_dma_tvalid(m_axis_dma_tvalid), 3590 3591 // VITA to Ethernet 3592 .v2e0_tdata(v2e0_tdata), 3593 .v2e0_tvalid(v2e0_tvalid), 3594 .v2e0_tlast(v2e0_tlast), 3595 .v2e0_tready(v2e0_tready), 3596 3597 .v2e1_tdata(v2e1_tdata), 3598 .v2e1_tlast(v2e1_tlast), 3599 .v2e1_tvalid(v2e1_tvalid), 3600 .v2e1_tready(v2e1_tready), 3601 3602 // Ethernet to VITA 3603 .e2v0_tdata(e2v0_tdata), 3604 .e2v0_tlast(e2v0_tlast), 3605 .e2v0_tvalid(e2v0_tvalid), 3606 .e2v0_tready(e2v0_tready), 3607 3608 .e2v1_tdata(e2v1_tdata), 3609 .e2v1_tlast(e2v1_tlast), 3610 .e2v1_tvalid(e2v1_tvalid), 3611 .e2v1_tready(e2v1_tready), 3612 3613 //regport interface to npio 3614 .reg_wr_req_npio(reg_wr_req_npio), 3615 .reg_wr_addr_npio(reg_wr_addr_npio), 3616 .reg_wr_data_npio(reg_wr_data_npio), 3617 .reg_rd_req_npio(reg_rd_req_npio), 3618 .reg_rd_addr_npio(reg_rd_addr_npio), 3619 .reg_rd_resp_npio(reg_rd_resp_npio), 3620 .reg_rd_data_npio(reg_rd_data_npio), 3621 3622 .build_datestamp(build_datestamp), 3623 .xadc_readback({20'h0, device_temp}), 3624 .sfp_ports_info({sfp_port1_info, sfp_port0_info}), 3625 .device_id(device_id) 3626 ); 3627 3628 // Register the ATR bits once between sending them out to the CPLD to avoid 3629 // glitches on the outputs! 3630 always @(posedge radio_clk) begin 3631 rx_atr_reg <= rx_atr; 3632 tx_atr_reg <= tx_atr; 3633 end 3634 3635 // ////////////////////////////////////////////////////////////////////// 3636 // 3637 // Daughterboard Cores 3638 // 3639 // ////////////////////////////////////////////////////////////////////// 3640 3641 wire sAdcSyncUnusedA; 3642 wire sAdcSyncUnusedB; 3643 wire sDacSyncUnusedA; 3644 wire sDacSyncUnusedB; 3645 wire sSysrefUnusedA; 3646 wire sSysrefUnusedB; 3647 wire rRpTransferUnusedA; 3648 wire rRpTransferUnusedB; 3649 wire sSpTransferUnusedA; 3650 wire sSpTransferUnusedB; 3651 wire rWrRpTransferUnusedA; 3652 wire rWrRpTransferUnusedB; 3653 wire sWrSpTransferUnusedA; 3654 wire sWrSpTransferUnusedB; 3655 wire sPpsUnusedB; 3656 wire sPpsToIobUnusedB; 3657 3658 wire dba_adc_sync_b; 3659 wire dba_dac_sync_b; 3660 wire dba_dac_sync_b_n; // This is the swapped version coming from the IBUFDS. 3661 wire dbb_adc_sync_b; 3662 wire dbb_dac_sync_b; 3663 3664 wire [49:0] bRegPortInFlatA; 3665 wire [49:0] bRegPortInFlatB; 3666 wire [33:0] bRegPortOutFlatA; 3667 wire [33:0] bRegPortOutFlatB; 3668 3669 wire rx_a_valid; 3670 wire rx_b_valid; 3671 wire tx_a_rfi; 3672 wire tx_b_rfi; 3673 3674`ifdef BUILD_WR 3675 localparam INCL_WR_TDC = 1'b1; 3676`else 3677 localparam INCL_WR_TDC = 1'b0; 3678`endif 3679 3680 wire reg_portA_rd; 3681 wire reg_portA_wr; 3682 wire [14-1:0] reg_portA_addr; 3683 wire [32-1:0] reg_portA_wr_data; 3684 wire [32-1:0] reg_portA_rd_data; 3685 wire reg_portA_ready; 3686 wire validA_unused; 3687 3688 OBUFDS dba_adc_sync_buf( 3689 .O(DBA_ADC_SYNCB_P), 3690 .OB(DBA_ADC_SYNCB_N), 3691 .I(dba_adc_sync_b) 3692 ); 3693 3694 IBUFDS dba_dac_sync_buf( 3695 .I(DBA_DAC_SYNCB_P), 3696 .IB(DBA_DAC_SYNCB_N), 3697 .O(dba_dac_sync_b_n) 3698 ); 3699 3700 // The differential signals are swapped in the pins, so the SYNC signal 3701 // must be negated after the IBUFDS. 3702 assign dba_dac_sync_b = ~ dba_dac_sync_b_n; 3703 3704 OBUFDS dbb_adc_sync_buf( 3705 .O(DBB_ADC_SYNCB_P), 3706 .OB(DBB_ADC_SYNCB_N), 3707 .I(dbb_adc_sync_b) 3708 ); 3709 3710 IBUFDS dbb_dac_sync_buf( 3711 .I(DBB_DAC_SYNCB_P), 3712 .IB(DBB_DAC_SYNCB_N), 3713 .O(dbb_dac_sync_b) 3714 ); 3715 3716 3717 assign bRegPortInFlatA = {2'b0, reg_portA_addr, reg_portA_wr_data, reg_portA_rd, reg_portA_wr}; 3718 assign {reg_portA_rd_data, validA_unused, reg_portA_ready} = bRegPortOutFlatA; 3719 3720 DbCore 3721 # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' 3722 dba_core ( 3723 .bBusReset(clk40_rst), //in std_logic 3724 .BusClk(clk40), //in std_logic 3725 .Clk40(clk40), //in std_logic 3726 .MeasClk(meas_clk), //in std_logic 3727 .FpgaClk_p(DBA_FPGA_CLK_P), //in std_logic 3728 .FpgaClk_n(DBA_FPGA_CLK_N), //in std_logic 3729 .SampleClk1xOut(radio_clk), //out std_logic 3730 .SampleClk1x(radio_clk), //in std_logic 3731 .SampleClk2xOut(radio_clk_2x), //out std_logic 3732 .SampleClk2x(radio_clk_2x), //in std_logic 3733 .bRegPortInFlat(bRegPortInFlatA), //in std_logic_vector(49:0) 3734 .bRegPortOutFlat(bRegPortOutFlatA), //out std_logic_vector(33:0) 3735 .kSlotId(1'b0), //in std_logic 3736 .sSysRefFpgaLvds_p(DBA_FPGA_SYSREF_P), //in std_logic 3737 .sSysRefFpgaLvds_n(DBA_FPGA_SYSREF_N), //in std_logic 3738 .aLmkSync(DBA_CLKDIST_SYNC), //out std_logic 3739 .JesdRefClk_p(DBA_MGTCLK_P), //in std_logic 3740 .JesdRefClk_n(DBA_MGTCLK_N), //in std_logic 3741 .aAdcRx_p(DBA_RX_P), //in std_logic_vector(3:0) 3742 .aAdcRx_n(DBA_RX_N), //in std_logic_vector(3:0) 3743 .aSyncAdcOut_n(dba_adc_sync_b), //out std_logic 3744 .aDacTx_p(DBA_TX_P), //out std_logic_vector(3:0) 3745 .aDacTx_n(DBA_TX_N), //out std_logic_vector(3:0) 3746 .aSyncDacIn_n(dba_dac_sync_b), //in std_logic 3747 .sAdcDataValid(rx_a_valid), //out std_logic 3748 .sAdcDataSample0I(rx_db[0][31:16]), //out std_logic_vector(15:0) 3749 .sAdcDataSample0Q(rx_db[0][15: 0]), //out std_logic_vector(15:0) 3750 .sAdcDataSample1I(rx_db[1][31:16]), //out std_logic_vector(15:0) 3751 .sAdcDataSample1Q(rx_db[1][15: 0]), //out std_logic_vector(15:0) 3752 .sDacReadyForInput(tx_a_rfi), //out std_logic 3753 .sDacDataSample0I(tx_db[0][31:16]), //in std_logic_vector(15:0) 3754 .sDacDataSample0Q(tx_db[0][15: 0]), //in std_logic_vector(15:0) 3755 .sDacDataSample1I(tx_db[1][31:16]), //in std_logic_vector(15:0) 3756 .sDacDataSample1Q(tx_db[1][15: 0]), //in std_logic_vector(15:0) 3757 .RefClk(ref_clk), //in std_logic 3758 .rPpsPulse(pps_refclk), //in std_logic 3759 .rGatedPulseToPin(UNUSED_PIN_TDCA_0), //inout std_logic 3760 .sGatedPulseToPin(UNUSED_PIN_TDCA_1), //inout std_logic 3761 .sPps(pps_radioclk1x), //out std_logic 3762 .sPpsToIob(pps_radioclk1x_iob), //out std_logic 3763 .WrRefClk(wr_ref_clk), //in std_logic 3764 .rWrPpsPulse(pps_wr_refclk), //in std_logic 3765 .rWrGatedPulseToPin(UNUSED_PIN_TDCA_2), //inout std_logic 3766 .sWrGatedPulseToPin(UNUSED_PIN_TDCA_3), //inout std_logic 3767 .aPpsSfpSel(pps_select_sfp), //in std_logic_vector(1:0) 3768 .sAdcSync(sAdcSyncUnusedA), //out std_logic 3769 .sDacSync(sDacSyncUnusedA), //out std_logic 3770 .sSysRef(sSysrefUnusedA), //out std_logic 3771 .rRpTransfer(rRpTransferUnusedA), //out std_logic 3772 .sSpTransfer(sSpTransferUnusedA), //out std_logic 3773 .rWrRpTransfer(rWrRpTransferUnusedA), //out std_logic 3774 .sWrSpTransfer(sWrSpTransferUnusedA)); //out std_logic 3775 3776 3777 3778 assign rx_stb[0] = rx_a_valid; 3779 assign tx_stb[0] = tx_a_rfi; 3780 3781 axil_to_ni_regport #( 3782 .RP_DWIDTH (32), 3783 .RP_AWIDTH (14), 3784 .TIMEOUT (512) 3785 ) ni_regportA_inst ( 3786 // Clock and reset 3787 .s_axi_aclk (clk40), 3788 .s_axi_areset (clk40_rst), 3789 // AXI4-Lite: Write address port (domain: s_axi_aclk) 3790 .s_axi_awaddr(M_AXI_JESD0_AWADDR), 3791 .s_axi_awvalid(M_AXI_JESD0_AWVALID), 3792 .s_axi_awready(M_AXI_JESD0_AWREADY), 3793 // AXI4-Lite: Write data port (domain: s_axi_aclk) 3794 .s_axi_wdata(M_AXI_JESD0_WDATA), 3795 .s_axi_wstrb(M_AXI_JESD0_WSTRB), 3796 .s_axi_wvalid(M_AXI_JESD0_WVALID), 3797 .s_axi_wready(M_AXI_JESD0_WREADY), 3798 // AXI4-Lite: Write response port (domain: s_axi_aclk) 3799 .s_axi_bresp(M_AXI_JESD0_BRESP), 3800 .s_axi_bvalid(M_AXI_JESD0_BVALID), 3801 .s_axi_bready(M_AXI_JESD0_BREADY), 3802 // AXI4-Lite: Read address port (domain: s_axi_aclk) 3803 .s_axi_araddr(M_AXI_JESD0_ARADDR), 3804 .s_axi_arvalid(M_AXI_JESD0_ARVALID), 3805 .s_axi_arready(M_AXI_JESD0_ARREADY), 3806 // AXI4-Lite: Read data port (domain: s_axi_aclk) 3807 .s_axi_rdata(M_AXI_JESD0_RDATA), 3808 .s_axi_rresp(M_AXI_JESD0_RRESP), 3809 .s_axi_rvalid(M_AXI_JESD0_RVALID), 3810 .s_axi_rready(M_AXI_JESD0_RREADY), 3811 // Register port 3812 .reg_port_in_rd (reg_portA_rd), 3813 .reg_port_in_wt (reg_portA_wr), 3814 .reg_port_in_addr (reg_portA_addr), 3815 .reg_port_in_data (reg_portA_wr_data), 3816 .reg_port_out_data (reg_portA_rd_data), 3817 .reg_port_out_ready(reg_portA_ready) 3818 ); 3819 3820 wire reg_portB_rd; 3821 wire reg_portB_wr; 3822 wire [14-1:0] reg_portB_addr; 3823 wire [32-1:0] reg_portB_wr_data; 3824 wire [32-1:0] reg_portB_rd_data; 3825 wire reg_portB_ready; 3826 wire validB_unused; 3827 3828 assign bRegPortInFlatB = {2'b0, reg_portB_addr, reg_portB_wr_data, reg_portB_rd, reg_portB_wr}; 3829 assign {reg_portB_rd_data, validB_unused, reg_portB_ready} = bRegPortOutFlatB; 3830 3831 DbCore 3832 # (.kInclWhiteRabbitTdc(INCL_WR_TDC)) //std_logic:='0' 3833 dbb_core ( 3834 .bBusReset(clk40_rst), //in std_logic 3835 .BusClk(clk40), //in std_logic 3836 .Clk40(clk40), //in std_logic 3837 .MeasClk(meas_clk), //in std_logic 3838 .FpgaClk_p(DBB_FPGA_CLK_P), //in std_logic 3839 .FpgaClk_n(DBB_FPGA_CLK_N), //in std_logic 3840 .SampleClk1xOut(radio_clkB), //out std_logic 3841 .SampleClk1x(radio_clk), //in std_logic 3842 .SampleClk2xOut(radio_clk_2xB), //out std_logic 3843 .SampleClk2x(radio_clk_2x), //in std_logic 3844 .bRegPortInFlat(bRegPortInFlatB), //in std_logic_vector(49:0) 3845 .bRegPortOutFlat(bRegPortOutFlatB), //out std_logic_vector(33:0) 3846 .kSlotId(1'b1), //in std_logic 3847 .sSysRefFpgaLvds_p(DBB_FPGA_SYSREF_P), //in std_logic 3848 .sSysRefFpgaLvds_n(DBB_FPGA_SYSREF_N), //in std_logic 3849 .aLmkSync(DBB_CLKDIST_SYNC), //out std_logic 3850 .JesdRefClk_p(DBB_MGTCLK_P), //in std_logic 3851 .JesdRefClk_n(DBB_MGTCLK_N), //in std_logic 3852 .aAdcRx_p(DBB_RX_P), //in std_logic_vector(3:0) 3853 .aAdcRx_n(DBB_RX_N), //in std_logic_vector(3:0) 3854 .aSyncAdcOut_n(dbb_adc_sync_b), //out std_logic 3855 .aDacTx_p(DBB_TX_P), //out std_logic_vector(3:0) 3856 .aDacTx_n(DBB_TX_N), //out std_logic_vector(3:0) 3857 .aSyncDacIn_n(dbb_dac_sync_b), //in std_logic 3858 .sAdcDataValid(rx_b_valid), //out std_logic 3859 .sAdcDataSample0I(rx_db[2][31:16]), //out std_logic_vector(15:0) 3860 .sAdcDataSample0Q(rx_db[2][15: 0]), //out std_logic_vector(15:0) 3861 .sAdcDataSample1I(rx_db[3][31:16]), //out std_logic_vector(15:0) 3862 .sAdcDataSample1Q(rx_db[3][15: 0]), //out std_logic_vector(15:0) 3863 .sDacReadyForInput(tx_b_rfi), //out std_logic 3864 .sDacDataSample0I(tx_db[2][31:16]), //in std_logic_vector(15:0) 3865 .sDacDataSample0Q(tx_db[2][15: 0]), //in std_logic_vector(15:0) 3866 .sDacDataSample1I(tx_db[3][31:16]), //in std_logic_vector(15:0) 3867 .sDacDataSample1Q(tx_db[3][15: 0]), //in std_logic_vector(15:0) 3868 .RefClk(ref_clk), //in std_logic 3869 .rPpsPulse(pps_refclk), //in std_logic 3870 .rGatedPulseToPin(UNUSED_PIN_TDCB_0), //inout std_logic 3871 .sGatedPulseToPin(UNUSED_PIN_TDCB_1), //inout std_logic 3872 .sPps(sPpsUnusedB), //out std_logic 3873 .sPpsToIob(sPpsToIobUnusedB), //out std_logic 3874 .WrRefClk(wr_ref_clk), //in std_logic 3875 .rWrPpsPulse(pps_wr_refclk), //in std_logic 3876 .rWrGatedPulseToPin(UNUSED_PIN_TDCB_2), //inout std_logic 3877 .sWrGatedPulseToPin(UNUSED_PIN_TDCB_3), //inout std_logic 3878 .aPpsSfpSel(2'd0), //in std_logic_vector(1:0) 3879 .sAdcSync(sAdcSyncUnusedB), //out std_logic 3880 .sDacSync(sDacSyncUnusedB), //out std_logic 3881 .sSysRef(sSysrefUnusedB), //out std_logic 3882 .rRpTransfer(rRpTransferUnusedB), //out std_logic 3883 .sSpTransfer(sSpTransferUnusedB), //out std_logic 3884 .rWrRpTransfer(rWrRpTransferUnusedB), //out std_logic 3885 .sWrSpTransfer(sWrSpTransferUnusedB)); //out std_logic 3886 3887 3888 3889 assign rx_stb[1] = rx_b_valid; 3890 assign tx_stb[1] = tx_b_rfi; 3891 3892 axil_to_ni_regport #( 3893 .RP_DWIDTH (32), 3894 .RP_AWIDTH (14), 3895 .TIMEOUT (512) 3896 ) ni_regportB_inst ( 3897 // Clock and reset 3898 .s_axi_aclk (clk40), 3899 .s_axi_areset (clk40_rst), 3900 // AXI4-Lite: Write address port (domain: s_axi_aclk) 3901 .s_axi_awaddr(M_AXI_JESD1_AWADDR), 3902 .s_axi_awvalid(M_AXI_JESD1_AWVALID), 3903 .s_axi_awready(M_AXI_JESD1_AWREADY), 3904 // AXI4-Lite: Write data port (domain: s_axi_aclk) 3905 .s_axi_wdata(M_AXI_JESD1_WDATA), 3906 .s_axi_wstrb(M_AXI_JESD1_WSTRB), 3907 .s_axi_wvalid(M_AXI_JESD1_WVALID), 3908 .s_axi_wready(M_AXI_JESD1_WREADY), 3909 // AXI4-Lite: Write response port (domain: s_axi_aclk) 3910 .s_axi_bresp(M_AXI_JESD1_BRESP), 3911 .s_axi_bvalid(M_AXI_JESD1_BVALID), 3912 .s_axi_bready(M_AXI_JESD1_BREADY), 3913 // AXI4-Lite: Read address port (domain: s_axi_aclk) 3914 .s_axi_araddr(M_AXI_JESD1_ARADDR), 3915 .s_axi_arvalid(M_AXI_JESD1_ARVALID), 3916 .s_axi_arready(M_AXI_JESD1_ARREADY), 3917 // AXI4-Lite: Read data port (domain: s_axi_aclk) 3918 .s_axi_rdata (M_AXI_JESD1_RDATA), 3919 .s_axi_rresp (M_AXI_JESD1_RRESP), 3920 .s_axi_rvalid (M_AXI_JESD1_RVALID), 3921 .s_axi_rready (M_AXI_JESD1_RREADY), 3922 // Register port 3923 .reg_port_in_rd (reg_portB_rd), 3924 .reg_port_in_wt (reg_portB_wr), 3925 .reg_port_in_addr (reg_portB_addr), 3926 .reg_port_in_data (reg_portB_wr_data), 3927 .reg_port_out_data (reg_portB_rd_data), 3928 .reg_port_out_ready(reg_portB_ready) 3929 ); 3930 3931 3932 // ////////////////////////////////////////////////////////////////////// 3933 // 3934 // LEDS 3935 // 3936 // ////////////////////////////////////////////////////////////////////// 3937 3938 assign PANEL_LED_LINK = ps_gpio_out[45]; 3939 assign PANEL_LED_REF = ps_gpio_out[46]; 3940 assign PANEL_LED_GPS = ps_gpio_out[47]; 3941 3942 3943 ///////////////////////////////////////////////////////////////////// 3944 // 3945 // PUDC Workaround 3946 // 3947 ////////////////////////////////////////////////////////////////////// 3948 // This is a workaround for a silicon bug in Series 7 FPGA where a 3949 // race condition with the reading of PUDC during the erase of the FPGA 3950 // image cause glitches on output IO pins. 3951 // 3952 // Workaround: 3953 // - Define the PUDC pin in the XDC file with a pullup. 3954 // - Implements an IBUF on the PUDC input and make sure that it does 3955 // not get optimized out. 3956 (* dont_touch = "true" *) wire fpga_pudc_b_buf; 3957 IBUF pudc_ibuf_i ( 3958 .I(FPGA_PUDC_B), 3959 .O(fpga_pudc_b_buf)); 3960 3961endmodule 3962