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Searched refs:clk_period (Results 1 – 25 of 338) sorted by relevance

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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/ticket14/
H A Dscrambler_tb.vhd9 constant clk_period : time := 10 ns; constant
31 wait for clk_period/2;
33 wait for clk_period/2;
43 wait for clk_period * 2;
45 wait for clk_period * 3.5;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug01/
H A Dtb.vhdl33 constant clk_period : time := 10 ns; constant
81 wait for clk_period/2;
83 wait for clk_period/2;
91 wait for clk_period*3;
100 wait for clk_period*5;
102 …wait for clk_period*4; --Appropriate amount of clock cycles needed for calculations to be displaye…
/dports/cad/ghdl/ghdl-1.0.0/testsuite/pyunit/lsp/files/
H A Dheartbeat.vhdl11 constant clk_period : time := 10 ns; constant
17 wait for clk_period/2;
19 wait for clk_period/2;
/dports/cad/ghdl/ghdl-1.0.0/doc/quick_start/simulation/heartbeat/
H A Dheartbeat.vhdl10 constant clk_period : time := 10 ns; constant
16 wait for clk_period/2;
18 wait for clk_period/2;
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c2290 clk_period /= 2; in calc_tdvw_max()
2301 clk_period /= 2; in calc_tdvw()
2343 dqs_sampl_res = clk_period / phony_dqs_mod; in cadence_nand_setup_interface()
2355 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_interface()
2356 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_interface()
2357 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_interface()
2386 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2400 trh_cnt = calc_cycl(trh, clk_period); in cadence_nand_setup_interface()
2436 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2444 if (sdr->tWC_min <= clk_period && in cadence_nand_setup_interface()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c2290 clk_period /= 2; in calc_tdvw_max()
2301 clk_period /= 2; in calc_tdvw()
2343 dqs_sampl_res = clk_period / phony_dqs_mod; in cadence_nand_setup_interface()
2355 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_interface()
2356 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_interface()
2357 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_interface()
2386 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2400 trh_cnt = calc_cycl(trh, clk_period); in cadence_nand_setup_interface()
2436 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2444 if (sdr->tWC_min <= clk_period && in cadence_nand_setup_interface()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c2290 clk_period /= 2; in calc_tdvw_max()
2301 clk_period /= 2; in calc_tdvw()
2343 dqs_sampl_res = clk_period / phony_dqs_mod; in cadence_nand_setup_interface()
2355 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_interface()
2356 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_interface()
2357 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_interface()
2386 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2400 trh_cnt = calc_cycl(trh, clk_period); in cadence_nand_setup_interface()
2436 + dqs_sampl_res) / clk_period; in cadence_nand_setup_interface()
2444 if (sdr->tWC_min <= clk_period && in cadence_nand_setup_interface()
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/sim/axis_pyld_ctxt_converter_tb/
H A Daxis_pyld_ctxt_converter_tb.sv41 realtime clk_period; member
51 '{clk_period: 6.0, item_w:64, nipc: 1, ctxt_fifo:5, pyld_fifo:7, prefetch:1},
52 '{clk_period:20.0, item_w:32, nipc: 6, ctxt_fifo:5, pyld_fifo:1, prefetch:1},
53 '{clk_period: 3.0, item_w:32, nipc: 4, ctxt_fifo:1, pyld_fifo:2, prefetch:0},
54 '{clk_period:10.0, item_w:16, nipc: 4, ctxt_fifo:8, pyld_fifo:5, prefetch:1},
55 '{clk_period: 3.0, item_w:32, nipc: 2, ctxt_fifo:1, pyld_fifo:7, prefetch:0},
56 '{clk_period: 3.0, item_w:8, nipc:13, ctxt_fifo:1, pyld_fifo:7, prefetch:0}
106 sim_clock_gen #(INST_PARAMS[inst_i].clk_period) dclk_gen (
115 .SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
151 .SYNC_CLKS (INST_PARAMS[inst_i].clk_period == CHDR_CLK_PERIOD),
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/mtd/nand/raw/
H A Dtegra_nand.c856 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
860 clk_period = 1000 / clk_rate; in setup_timing()
861 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
863 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
865 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
869 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
875 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
877 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
879 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
881 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/mtd/nand/raw/
H A Dtegra_nand.c856 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
860 clk_period = 1000 / clk_rate; in setup_timing()
861 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
863 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
865 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
869 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
875 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
877 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
879 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
881 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/mtd/nand/raw/
H A Dtegra_nand.c856 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
860 clk_period = 1000 / clk_rate; in setup_timing()
861 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
863 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
865 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
869 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
875 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
877 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
879 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
881 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dtegra_nand.c861 u32 reg_val, clk_rate, clk_period, time_val; in setup_timing() local
865 clk_period = 1000 / clk_rate; in setup_timing()
866 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
868 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) << in setup_timing()
870 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period; in setup_timing()
874 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) << in setup_timing()
880 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) << in setup_timing()
882 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) << in setup_timing()
884 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) << in setup_timing()
886 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) << in setup_timing()
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