/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
H A D | ctrlport_endpoint.v | 34 input wire ctrlport_clk, port 92 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0), 101 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0), 114 .o_aclk(ctrlport_clk), 121 .i_aclk(ctrlport_clk), 151 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0), 166 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0), 211 .clk (ctrlport_clk), 244 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0), 253 .clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/ |
H A D | ctrlport_terminator.v | 17 input wire ctrlport_clk, port 34 always @(posedge ctrlport_clk) begin 35 if (ctrlport_clk) begin
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H A D | ctrlport_reg_rw.v | 65 input wire ctrlport_clk, port 139 always @(posedge ctrlport_clk) begin 186 always @(posedge ctrlport_clk) begin 229 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_reg_ro.v | 59 input wire ctrlport_clk, port 139 always @(posedge ctrlport_clk) begin 165 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_combiner.v | 36 input wire ctrlport_clk, port 112 always @(posedge ctrlport_clk) begin 167 always @(posedge ctrlport_clk) begin 220 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_decoder_param.v | 58 input wire ctrlport_clk, port 114 always @(posedge ctrlport_clk) begin 160 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_decoder.v | 42 input wire ctrlport_clk, port 96 always @(posedge ctrlport_clk) begin 143 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_resp_combine.v | 29 input wire ctrlport_clk, port 43 always @(posedge ctrlport_clk) begin
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H A D | ctrlport_gate.v | 15 input wire ctrlport_clk, port 54 always @(posedge ctrlport_clk) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/ |
H A D | ctrlport_endpoint_tb.sv | 32 bit ctrlport_clk, ctrlport_rst; register 35 sim_clock_gen #(20.0) ctrlport_clk_gen (ctrlport_clk, ctrlport_rst); // 50 MHz 83 .ctrlport_clk (ctrlport_clk ), 161 always @(posedge ctrlport_clk) begin 227 @(posedge ctrlport_clk); 230 while (~cp_mst_resp_ack) @(posedge ctrlport_clk); 373 while (ctrlport_rst) @(posedge ctrlport_clk);
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/examples/rfnoc-example/fpga/rfnoc_block_gain/ |
H A D | rfnoc_block_gain.v | 63 wire ctrlport_clk; net 147 .ctrlport_clk (ctrlport_clk), 215 always @(posedge ctrlport_clk) begin
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H A D | noc_shell_gain.v | 71 output wire ctrlport_clk, port 150 assign ctrlport_clk = rfnoc_chdr_clk; 162 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/ |
H A D | rfnoc_block_keep_one_in_n.v | 67 wire ctrlport_clk; net 142 .ctrlport_clk (ctrlport_clk), 187 .ctrlport_clk (ctrlport_clk),
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H A D | noc_shell_keep_one_in_n.v | 74 output wire ctrlport_clk, port 167 assign ctrlport_clk = ce_clk; 179 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/ |
H A D | noc_shell_switchboard.v | 73 output wire ctrlport_clk, port 138 assign ctrlport_clk = rfnoc_chdr_clk; 150 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/ |
H A D | noc_shell_siggen.v | 74 output wire ctrlport_clk, port 156 assign ctrlport_clk = ce_clk; 168 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/ |
H A D | noc_shell_axi_ram_fifo.v | 79 output wire ctrlport_clk, port 160 assign ctrlport_clk = mem_clk; 172 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/ |
H A D | noc_shell_fft.v | 77 output wire ctrlport_clk, port 172 assign ctrlport_clk = ce_clk; 184 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/ |
H A D | noc_shell_duc.v | 76 output wire ctrlport_clk, port 170 assign ctrlport_clk = ce_clk; 182 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/ |
H A D | noc_shell_moving_avg.v | 74 output wire ctrlport_clk, port 169 assign ctrlport_clk = ce_clk; 181 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/ |
H A D | noc_shell_window.v | 75 output wire ctrlport_clk, port 170 assign ctrlport_clk = ce_clk; 182 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/ |
H A D | noc_shell_fosphor.v | 73 output wire ctrlport_clk, port 177 assign ctrlport_clk = ce_clk; 189 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/ |
H A D | noc_shell_vector_iir.v | 74 output wire ctrlport_clk, port 169 assign ctrlport_clk = ce_clk; 181 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/ |
H A D | noc_shell_ddc.v | 76 output wire ctrlport_clk, port 170 assign ctrlport_clk = ce_clk; 182 .ctrlport_clk (ctrlport_clk),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/ |
H A D | noc_shell_fir_filter.v | 81 output wire ctrlport_clk, port 176 assign ctrlport_clk = ce_clk; 188 .ctrlport_clk (ctrlport_clk),
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