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Searched refs:ctrlport_clk (Results 1 – 25 of 59) sorted by relevance

123

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/
H A Dctrlport_endpoint.v34 input wire ctrlport_clk, port
92 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
101 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
114 .o_aclk(ctrlport_clk),
121 .i_aclk(ctrlport_clk),
151 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
166 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
211 .clk (ctrlport_clk),
244 .clk(ctrlport_clk), .reset(ctrlport_rst), .clear(1'b0),
253 .clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/
H A Dctrlport_terminator.v17 input wire ctrlport_clk, port
34 always @(posedge ctrlport_clk) begin
35 if (ctrlport_clk) begin
H A Dctrlport_reg_rw.v65 input wire ctrlport_clk, port
139 always @(posedge ctrlport_clk) begin
186 always @(posedge ctrlport_clk) begin
229 always @(posedge ctrlport_clk) begin
H A Dctrlport_reg_ro.v59 input wire ctrlport_clk, port
139 always @(posedge ctrlport_clk) begin
165 always @(posedge ctrlport_clk) begin
H A Dctrlport_combiner.v36 input wire ctrlport_clk, port
112 always @(posedge ctrlport_clk) begin
167 always @(posedge ctrlport_clk) begin
220 always @(posedge ctrlport_clk) begin
H A Dctrlport_decoder_param.v58 input wire ctrlport_clk, port
114 always @(posedge ctrlport_clk) begin
160 always @(posedge ctrlport_clk) begin
H A Dctrlport_decoder.v42 input wire ctrlport_clk, port
96 always @(posedge ctrlport_clk) begin
143 always @(posedge ctrlport_clk) begin
H A Dctrlport_resp_combine.v29 input wire ctrlport_clk, port
43 always @(posedge ctrlport_clk) begin
H A Dctrlport_gate.v15 input wire ctrlport_clk, port
54 always @(posedge ctrlport_clk) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/sim/ctrlport_endpoint_tb/
H A Dctrlport_endpoint_tb.sv32 bit ctrlport_clk, ctrlport_rst; register
35 sim_clock_gen #(20.0) ctrlport_clk_gen (ctrlport_clk, ctrlport_rst); // 50 MHz
83 .ctrlport_clk (ctrlport_clk ),
161 always @(posedge ctrlport_clk) begin
227 @(posedge ctrlport_clk);
230 while (~cp_mst_resp_ack) @(posedge ctrlport_clk);
373 while (ctrlport_rst) @(posedge ctrlport_clk);
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/examples/rfnoc-example/fpga/rfnoc_block_gain/
H A Drfnoc_block_gain.v63 wire ctrlport_clk; net
147 .ctrlport_clk (ctrlport_clk),
215 always @(posedge ctrlport_clk) begin
H A Dnoc_shell_gain.v71 output wire ctrlport_clk, port
150 assign ctrlport_clk = rfnoc_chdr_clk;
162 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/
H A Drfnoc_block_keep_one_in_n.v67 wire ctrlport_clk; net
142 .ctrlport_clk (ctrlport_clk),
187 .ctrlport_clk (ctrlport_clk),
H A Dnoc_shell_keep_one_in_n.v74 output wire ctrlport_clk, port
167 assign ctrlport_clk = ce_clk;
179 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/
H A Dnoc_shell_switchboard.v73 output wire ctrlport_clk, port
138 assign ctrlport_clk = rfnoc_chdr_clk;
150 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/
H A Dnoc_shell_siggen.v74 output wire ctrlport_clk, port
156 assign ctrlport_clk = ce_clk;
168 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/
H A Dnoc_shell_axi_ram_fifo.v79 output wire ctrlport_clk, port
160 assign ctrlport_clk = mem_clk;
172 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/
H A Dnoc_shell_fft.v77 output wire ctrlport_clk, port
172 assign ctrlport_clk = ce_clk;
184 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/
H A Dnoc_shell_duc.v76 output wire ctrlport_clk, port
170 assign ctrlport_clk = ce_clk;
182 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/
H A Dnoc_shell_moving_avg.v74 output wire ctrlport_clk, port
169 assign ctrlport_clk = ce_clk;
181 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/
H A Dnoc_shell_window.v75 output wire ctrlport_clk, port
170 assign ctrlport_clk = ce_clk;
182 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/
H A Dnoc_shell_fosphor.v73 output wire ctrlport_clk, port
177 assign ctrlport_clk = ce_clk;
189 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/
H A Dnoc_shell_vector_iir.v74 output wire ctrlport_clk, port
169 assign ctrlport_clk = ce_clk;
181 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/
H A Dnoc_shell_ddc.v76 output wire ctrlport_clk, port
170 assign ctrlport_clk = ce_clk;
182 .ctrlport_clk (ctrlport_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/
H A Dnoc_shell_fir_filter.v81 output wire ctrlport_clk, port
176 assign ctrlport_clk = ce_clk;
188 .ctrlport_clk (ctrlport_clk),

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