1// 2// Copyright 2019 Ettus Research, A National Instruments Company 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6// Module: ctrlport_terminator.v 7// Description: 8// Returns an error for all ctrlport requests in given address range. 9 10module ctrlport_terminator #( 11 parameter START_ADDRESS = 0, // first address to generate response for 12 parameter LAST_ADDRESS = 32 // last address (including) to generate response for 13)( 14 //--------------------------------------------------------------- 15 // ControlPort slave 16 //--------------------------------------------------------------- 17 input wire ctrlport_clk, 18 input wire ctrlport_rst, 19 input wire s_ctrlport_req_wr, 20 input wire s_ctrlport_req_rd, 21 input wire [19:0] s_ctrlport_req_addr, 22 input wire [31:0] s_ctrlport_req_data, 23 24 output reg s_ctrlport_resp_ack, 25 output wire [ 1:0] s_ctrlport_resp_status, 26 output wire [31:0] s_ctrlport_resp_data 27); 28 29`include "../core/ctrlport.vh" 30//vhook_nowarn s_ctrlport_req_addr 31//vhook_nowarn s_ctrlport_req_data 32 33// drive acknowledgement on requests but not on reset 34always @(posedge ctrlport_clk) begin 35 if (ctrlport_clk) begin 36 if (ctrlport_rst) begin 37 s_ctrlport_resp_ack <= 1'b0; 38 end else if ((s_ctrlport_req_addr >= START_ADDRESS) && (s_ctrlport_req_addr <= LAST_ADDRESS)) begin 39 s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd; 40 end else begin 41 s_ctrlport_resp_ack <= 1'b0; 42 end 43 end 44end 45 46// other outputs are fixed 47assign s_ctrlport_resp_status = CTRL_STS_CMDERR; 48assign s_ctrlport_resp_data = { CTRLPORT_DATA_W {1'b0}}; 49 50endmodule