/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2405 surf->db_htile_surface = 0; in si_init_depth_surface() 2445 surf->db_htile_surface = in si_init_depth_surface() 2448 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2516 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3112 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3207 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3240 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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H A D | r600_state.c | 1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface() 1556 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state() 1561 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state() 1606 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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H A D | r600_state.c | 1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface() 1556 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state() 1561 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state() 1606 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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H A D | r600_state.c | 1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface() 1556 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state() 1561 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state() 1606 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 277 unsigned db_htile_surface; member
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 282 unsigned db_htile_surface; member
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/r600/ |
H A D | r600_pipe_common.h | 284 unsigned db_htile_surface; member
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2572 surf->db_htile_surface = 0; in si_init_depth_surface() 2610 surf->db_htile_surface = in si_init_depth_surface() 2613 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2682 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3298 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3381 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3414 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 2554 surf->db_htile_surface = 0; in si_init_depth_surface() 2592 surf->db_htile_surface = in si_init_depth_surface() 2595 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface() 2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface() 3274 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local 3348 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state() 3381 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
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