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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_order_doubleloop.v26 reg [31:0] dlyrun; initial dlyrun = 0; register
38 dlyrun <= 5;
86 if (dlyrun > 0) begin
87 dlyrun <= dlyrun - 32'd1;
89 $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1);