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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_math_repl.v28 wire [31:0] dualasr net
60 $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep);
79 if (dualasr != 32'h8f1f7060) $stop;
93 if (dualasr != 32'h0000ffff) $stop;
101 if (dualasr != 32'h3062cc1e) $stop;