1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2004 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (/*AUTOARG*/
8   // Inputs
9   clk
10   );
11
12   input clk;
13   integer cyc; initial cyc=1;
14
15   reg [63:0] rf;
16   reg [63:0] rf2;
17   reg [63:0] biu;
18   reg	      b;
19
20   always @* begin
21      rf[63:32] = biu[63:32] & {32{b}};
22      rf[31:0]  = {32{b}};
23      rf2 = rf;
24      rf2[31:0]  = ~{32{b}};
25   end
26
27   reg  [31:0] src1, src0, sr, mask;
28   wire [31:0] dualasr
29	       = ((| src1[31:4])
30		  ? {{16{src0[31]}}, {16{src0[15]}}}
31		  : (  (  sr & {2{mask[31:16]}})
32		       | (  {{16{src0[31]}}, {16{src0[15]}}}
33			    & {2{~mask[31:16]}})));
34
35   wire [31:0] sl_mask
36	       = (32'hffffffff << src1[4:0]);
37
38   wire [31:0] sr_mask
39	       = {sl_mask[0],  sl_mask[1],
40		  sl_mask[2],  sl_mask[3],  sl_mask[4],
41                  sl_mask[5],  sl_mask[6],  sl_mask[7],
42		  sl_mask[8],  sl_mask[9],
43                  sl_mask[10], sl_mask[11],
44		  sl_mask[12], sl_mask[13], sl_mask[14],
45                  sl_mask[15], sl_mask[16],
46		  sl_mask[17], sl_mask[18], sl_mask[19],
47                  sl_mask[20], sl_mask[21],
48		  sl_mask[22], sl_mask[23], sl_mask[24],
49                  sl_mask[25], sl_mask[26],
50		  sl_mask[27], sl_mask[28], sl_mask[29],
51                  sl_mask[30], sl_mask[31]};
52
53   wire [95:0]  widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}};
54   wire [1:0] 	w = {2{b}};
55
56   always @ (posedge clk) begin
57      if (cyc!=0) begin
58	 cyc <= cyc + 1;
59`ifdef TEST_VERBOSE
60	 $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep);
61`endif
62	 if (cyc==1) begin
63	    biu <= 64'h12451282_abadee00;
64	    b <= 1'b0;
65	    src1 <= 32'h00000001;
66	    src0 <= 32'h9a4f1235;
67	    sr   <= 32'h0f19f567;
68	    mask <= 32'h7af07ab4;
69	 end
70	 if (cyc==2) begin
71	    biu <= 64'h12453382_abad8801;
72	    b <= 1'b1;
73	    if (rf != 64'h0) $stop;
74	    if (rf2 != 64'h00000000ffffffff) $stop;
75	    src1 <= 32'h0010000f;
76	    src0 <= 32'h028aa336;
77	    sr   <= 32'h42ad0377;
78	    mask <= 32'h1ab3b906;
79	    if (dualasr != 32'h8f1f7060) $stop;
80	    if (sl_mask != 32'hfffffffe) $stop;
81	    if (sr_mask != 32'h7fffffff) $stop;
82	    if (widerep != '0) $stop;
83	 end
84	 if (cyc==3) begin
85	    biu <= 64'h12422382_77ad8802;
86	    b <= 1'b1;
87	    if (rf != 64'h12453382ffffffff) $stop;
88	    if (rf2 != 64'h1245338200000000) $stop;
89	    src1 <= 32'h0000000f;
90	    src0 <= 32'h5c158f71;
91	    sr   <= 32'h7076c40a;
92	    mask <= 32'h33eb3d44;
93	    if (dualasr != 32'h0000ffff) $stop;
94	    if (sl_mask != 32'hffff8000) $stop;
95	    if (sr_mask != 32'h0001ffff) $stop;
96	    if (widerep != '1) $stop;
97	 end
98	 if (cyc==4) begin
99	    if (rf != 64'h12422382ffffffff) $stop;
100	    if (rf2 != 64'h1242238200000000) $stop;
101	    if (dualasr != 32'h3062cc1e) $stop;
102	    if (sl_mask != 32'hffff8000) $stop;
103	    if (sr_mask != 32'h0001ffff) $stop;
104	    $write("*-* All Finished *-*\n");
105	    if (widerep != '1) $stop;
106	    $finish;
107	 end
108      end
109   end
110endmodule
111