| /dports/devel/p5-Data-Dump-Streamer/Data-Dump-Streamer-2.40/t/ |
| H A D | test_helper.pl | 219 my $dumpvars=join ( ",", @dump );
229 my $result2_eval = $result . "\n" . 'scalar( $obj->Data(' . $dumpvars . ")->Out())\n";
232 . 'sub{\@_}->(' . $dumpvars . ")"
304 my $dumpvars=join ( ",", @dump );
314 my $result2_eval = $result . "\n" . 'scalar( $obj->Data(' . $dumpvars . ")->Out())\n";
317 . 'sub{\@_}->(' . $dumpvars . ")"
|
| /dports/cad/iverilog/verilog-11.0/examples/ |
| H A D | show_vcd.vl | 60 * $dumpvars system tasks. The $dumpfile task tells the simulation where
62 * $dumpvars task is called.
64 * The $dumpvars task tells the simulation what variables to write to
96 $dumpvars(1, main.r1);
|
| /dports/lang/perl5.34/perl-5.34.0/dist/Dumpvalue/t/ |
| H A D | Dumpvalue.t | 239 $d->dumpvars( 'Fake', 'veryfake' );
244 $d->dumpvars( 'main', 'INC' );
249 $d->dumpvars( 'main', 'INC' );
|
| H A D | extend-coverage.t | 262 $d->dumpvars( 'Fake', 'veryfake' );
267 $e->dumpvars( 'Fake', 'veryfake' );
272 $f->dumpvars( 'main', 'INC' );
277 $g->dumpvars( 'main', 'INC' );
288 $h->dumpvars( 'main', 'INC' );
293 $i->dumpvars( 'main', 'INC' );
303 $j->dumpvars( 'main', 'INC' );
308 $k->dumpvars( 'main', 'INC' );
313 $l->dumpvars( 'main::', 'INC' );
|
| /dports/lang/perl5.32/perl-5.32.1/dist/Dumpvalue/t/ |
| H A D | Dumpvalue.t | 235 $d->dumpvars( 'Fake', 'veryfake' );
240 $d->dumpvars( 'main', 'INC' );
245 $d->dumpvars( 'main', 'INC' );
|
| H A D | extend-coverage.t | 262 $d->dumpvars( 'Fake', 'veryfake' );
267 $e->dumpvars( 'Fake', 'veryfake' );
272 $f->dumpvars( 'main', 'INC' );
277 $g->dumpvars( 'main', 'INC' );
288 $h->dumpvars( 'main', 'INC' );
293 $i->dumpvars( 'main', 'INC' );
303 $j->dumpvars( 'main', 'INC' );
308 $k->dumpvars( 'main', 'INC' );
313 $l->dumpvars( 'main::', 'INC' );
|
| /dports/lang/perl5-devel/perl5-5.35.4-102-ge43d289c7c/dist/Dumpvalue/t/ |
| H A D | Dumpvalue.t | 239 $d->dumpvars( 'Fake', 'veryfake' );
244 $d->dumpvars( 'main', 'INC' );
249 $d->dumpvars( 'main', 'INC' );
|
| H A D | extend-coverage.t | 262 $d->dumpvars( 'Fake', 'veryfake' );
267 $e->dumpvars( 'Fake', 'veryfake' );
272 $f->dumpvars( 'main', 'INC' );
277 $g->dumpvars( 'main', 'INC' );
288 $h->dumpvars( 'main', 'INC' );
293 $i->dumpvars( 'main', 'INC' );
303 $j->dumpvars( 'main', 'INC' );
308 $k->dumpvars( 'main', 'INC' );
313 $l->dumpvars( 'main::', 'INC' );
|
| /dports/lang/perl5.30/perl-5.30.3/dist/Dumpvalue/t/ |
| H A D | Dumpvalue.t | 233 $d->dumpvars( 'Fake', 'veryfake' );
238 $d->dumpvars( 'main', 'INC' );
243 $d->dumpvars( 'main', 'INC' );
|
| /dports/misc/dejagnu/dejagnu-1.6.3/lib/ |
| H A D | debugger.exp | 23 proc dumpvars { args } { procedure
201 uplevel 1 dumpvars $args
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/dejagnu/lib/ |
| H A D | debugger.exp | 25 proc dumpvars { args } { procedure
211 uplevel 1 dumpvars $args
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/dejagnu/lib/ |
| H A D | debugger.exp | 25 proc dumpvars { args } { procedure
211 uplevel 1 dumpvars $args
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/functional/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /b205_clk_gen_tb -l 0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/b205_clk_gen/simulation/timing/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /b205_clk_gen_tb -l 0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/functional/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /b200_clk_gen_tb -l 0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_clk_gen/simulation/timing/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /b200_clk_gen_tb -l 0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/coregen/pll_100_40_75/simulation/functional/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /pll_100_40_75_tb -l 0
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/coregen/pll_100_40_75/simulation/timing/ |
| H A D | simcmds.tcl | 5 vcd dumpvars -m /pll_100_40_75_tb -l 0
|
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_trace_abort_fst_sc.out | 19 $dumpvars
|
| H A D | t_trace_abort_fst.out | 20 $dumpvars
|
| H A D | t_trace_packed_struct_fst_sc.out | 22 $dumpvars
|
| H A D | t_trace_packed_struct_fst.out | 23 $dumpvars
|
| H A D | t_trace_array_fst_sc.out | 22 $dumpvars
|
| H A D | t_trace_array_fst.out | 23 $dumpvars
|
| /dports/cad/dinotrace/dinotrace-9.4c/traces/ |
| H A D | vcd.vcd | 22 $dumpvars
|