1$date 2 Thu Apr 1 14:55:09 2021 3 4$end 5$version 6 fstWriter 7$end 8$timescale 9 1ps 10$end 11$scope module top $end 12$scope module t $end 13$var wire 1 ! clk $end 14$var logic 3 " cyc $end 15$upscope $end 16$upscope $end 17$enddefinitions $end 18#0 19$dumpvars 20b000 " 210! 22$end 23#10 241! 25b001 " 26#11 27#12 28#13 29#14 30#15 310! 32#16 33#17 34#18 35#19 36#20 371! 38b010 " 39#21 40#22 41#23 42#24 43#25 440! 45#26 46#27 47#28 48#29 49#30 501! 51b011 " 52#31 53#32 54#33 55#34 56#35 570! 58#36 59#37 60#38 61#39 62#40 631! 64b100 " 65#41 66#42 67#43 68#44 69#45 700! 71#46 72#47 73#48 74#49 75#50 761! 77b101 " 78#51 79#52 80#53 81#54 82#55 830! 84#56 85#57 86#58 87#59 88#60 891! 90b110 " 91#61 92#62 93#63 94#64 95#65 960! 97#66 98#67 99#68 100#69 101#70 1021! 103b111 " 104#71 105#72 106#73 107#74 108#75 1090! 110#76 111#77 112#78 113#79 114