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/dports/devel/hs-spago/spago-0.20.3/_cabal_deps/dhall-1.38.1/tests/format/
H A DdoubleRoundA.dhall12 , 1.0000000000000000e64
13 , 1.0000000000000001e64
14 , 1.0000000000000002e64
15 , 1.0000000000000003e64
16 , 1.0000000000000004e64
17 , 1.0000000000000005e64
18 , 1.0000000000000006e64
19 , 1.0000000000000007e64
20 , 1.0000000000000008e64
21 , 1.0000000000000009e64
H A DdoubleRoundB.dhall11 , 1.0000000000000000e64
12 , 1.0000000000000001e64
13 , 1.0000000000000002e64
14 , 1.0000000000000003e64
15 , 1.0000000000000004e64
16 , 1.0000000000000005e64
17 , 1.0000000000000006e64
18 , 1.0000000000000007e64
19 , 1.0000000000000008e64
20 , 1.0000000000000009e64
/dports/devel/chrpath/chrpath-0.16/
H A Dprotos.h33 Elf64_Ehdr e64; member
38 Elf64_Shdr e64; member
43 Elf64_Phdr e64; member
56 #define EHDRWS(x) (is_e32() ? DO_SWAPS32(ehdr.e32.x) : DO_SWAPS64(ehdr.e64.x))
57 #define EHDRHS(x) (is_e32() ? DO_SWAPS16(ehdr.e32.x) : DO_SWAPS16(ehdr.e64.x))
58 #define EHDRWU(x) (is_e32() ? DO_SWAPU32(ehdr.e32.x) : DO_SWAPU64(ehdr.e64.x))
59 #define EHDRHU(x) (is_e32() ? DO_SWAPU16(ehdr.e32.x) : DO_SWAPU16(ehdr.e64.x))
60 #define PHDR(x) (is_e32() ? DO_SWAPU32(phdr.e32.x) : DO_SWAPU64(phdr.e64.x))
61 #define SHDR_W(x) (is_e32() ? DO_SWAPU32(shdr.e32.x) : DO_SWAPU32(shdr.e64.x))
62 #define SHDR_O(x) (is_e32() ? DO_SWAPU32(shdr.e32.x) : DO_SWAPU64(shdr.e64.x))
H A Delf.c19 #define EHDR_PWS(x) (is_e32() ? DO_SWAPS32(ehdr->e32.x) : DO_SWAPS64(ehdr->e64.x))
20 #define EHDR_PHS(x) (is_e32() ? DO_SWAPS16(ehdr->e32.x) : DO_SWAPS16(ehdr->e64.x))
21 #define PHDR_PWS(x) (is_e32() ? DO_SWAPS32(phdr->e32.x) : DO_SWAPS64(phdr->e64.x))
22 #define EHDR_PWU(x) (is_e32() ? DO_SWAPU32(ehdr->e32.x) : DO_SWAPU64(ehdr->e64.x))
23 #define EHDR_PHU(x) (is_e32() ? DO_SWAPU16(ehdr->e32.x) : DO_SWAPU16(ehdr->e64.x))
24 #define PHDR_PWU(x) (is_e32() ? DO_SWAPU32(phdr->e32.x) : DO_SWAPU32(phdr->e64.x))
25 #define PHDR_POU(x) (is_e32() ? DO_SWAPU32(phdr->e32.x) : DO_SWAPU64(phdr->e64.x))
/dports/devel/elfutils/elfutils-0.179/libdwfl/
H A Delf-from-memory.c106 Elf64_Ehdr e64; in elf_from_remote_memory() member
154 phoff = ehdr.e64.e_phoff; in elf_from_remote_memory()
155 phnum = ehdr.e64.e_phnum; in elf_from_remote_memory()
156 phentsize = ehdr.e64.e_phentsize; in elf_from_remote_memory()
160 shdrs_end = ehdr.e64.e_shoff + ehdr.e64.e_shnum * ehdr.e64.e_shentsize; in elf_from_remote_memory()
269 ehdr.e64.e_ident[EI_DATA]) == NULL) in elf_from_remote_memory()
363 ehdr.e64.e_shoff = 0; in elf_from_remote_memory()
364 ehdr.e64.e_shnum = 0; in elf_from_remote_memory()
365 ehdr.e64.e_shstrndx = 0; in elf_from_remote_memory()
372 xlatefrom.d_buf = &ehdr.e64; in elf_from_remote_memory()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-insert.ll11 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
17 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
19 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
25 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
28 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
30 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
46 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
50 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
58 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
64 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
[all …]
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
69 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
80 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
103 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-fp-shuffles.ll39 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
50 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
65 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
76 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
99 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
124 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
156 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
162 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
195 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
220 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-insert.ll11 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
17 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
19 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
25 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
28 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
30 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
46 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
50 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
58 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
64 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
[all …]
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
69 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
80 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
103 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-fp-shuffles.ll39 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
50 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
65 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
76 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
99 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
124 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
156 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
162 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
195 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
220 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-insert.ll11 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
17 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
19 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
25 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
28 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
30 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
46 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
50 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
58 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
64 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
[all …]
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
69 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
80 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
103 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-fp-shuffles.ll39 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
50 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
65 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
76 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
99 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
124 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
156 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
162 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
195 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
220 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-insert.ll11 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
17 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
19 ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
25 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
28 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
30 ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, mu
46 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
50 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
58 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
64 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
[all …]
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
69 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
80 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
103 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-fp-shuffles.ll39 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
50 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
65 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
76 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
99 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
124 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
156 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
162 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
195 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
220 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-insert.ll11 ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
17 ; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu
24 ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
27 ; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
44 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
48 ; RV32-NEXT: vsetivli zero, 2, e64, m2, tu, mu
56 ; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu
62 ; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu
66 ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
180 ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
[all …]
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
69 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
80 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
103 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-bitcast.ll81 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
89 ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
100 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
108 ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
119 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
127 ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
138 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
146 ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
207 ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
215 ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, mu
[all …]
/dports/devel/etcd/etcd-2.3.8/Godeps/_workspace/src/github.com/prometheus/common/expfmt/testdata/
H A Dprotobuf12 0a12 0a07 6861 6e64 6c65 7212 072f 616c
61 0a07 6861 6e64 6c65 7212 082f 7374 6174
67 0a07 6861 6e64 6c65 7212 0a70 726f 6d65
82 0000 0000 0000 225d 0a12 0a07 6861 6e64
131 0000 0000 225e 0a13 0a07 6861 6e64 6c65
137 0000 0000 2260 0a15 0a07 6861 6e64 6c65
148 3030 0a15 0a07 6861 6e64 6c65 7212 0a70
155 732e 1802 2257 0a0c 0a07 6861 6e64 6c65
167 0a07 6861 6e64 6c65 7212 0c2f 6170 692f
173 2260 0a15 0a07 6861 6e64 6c65 7212 0a2f
[all …]
/dports/print/lilypond-devel/lilypond-2.23.5/input/regression/
H A Drepeat-tremolo-beams.ly9 \repeat tremolo 8 { c64 e64 }
10 \repeat tremolo 12 { c64 e64 }
11 \repeat tremolo 14 { c64 e64 }
12 \repeat tremolo 15 { c64 e64 }
/dports/print/lilypond/lilypond-2.22.1/input/regression/
H A Drepeat-tremolo-beams.ly9 \repeat tremolo 8 { c64 e64 }
10 \repeat tremolo 12 { c64 e64 }
11 \repeat tremolo 14 { c64 e64 }
12 \repeat tremolo 15 { c64 e64 }
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
65 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
77 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
88 ; RV32V-NEXT: vsetvli a2, zero, e64,m8,ta,mu
100 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/RISCV/rvv/
H A Dvsplats-i64.ll10 ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
16 ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
27 ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
33 ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu
45 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
52 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
65 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
77 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
88 ; RV32V-NEXT: vsetvli a2, zero, e64,m8,ta,mu
100 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu
[all …]

12345678910>>...127