| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 84 MachineInstr *emitScalarToVector(unsigned EltSize,
2448 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
2590 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3045 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3047 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
3371 MachineInstr *Widen = emitScalarToVector( in tryOptVectorDup()
3458 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
3509 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3556 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
3615 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 99 MachineInstr *emitScalarToVector(unsigned EltSize,
2778 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
2944 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3402 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3404 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
3750 MachineInstr *Widen = emitScalarToVector( in tryOptVectorDup()
3829 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3927 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
3986 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 99 MachineInstr *emitScalarToVector(unsigned EltSize,
2778 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
2944 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3402 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3404 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
3750 MachineInstr *Widen = emitScalarToVector( in tryOptVectorDup()
3829 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3927 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
3986 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 99 MachineInstr *emitScalarToVector(unsigned EltSize,
2778 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
2944 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3402 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3404 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
3750 MachineInstr *Widen = emitScalarToVector( in tryOptVectorDup()
3829 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3927 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
3986 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 117 MachineInstr *emitScalarToVector(unsigned EltSize,
3351 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3517 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4032 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4034 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4375 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4425 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4472 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
4591 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 114 MachineInstr *emitScalarToVector(unsigned EltSize,
3251 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3417 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3877 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3879 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4351 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4401 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4448 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
4548 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 114 MachineInstr *emitScalarToVector(unsigned EltSize,
3252 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3418 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
3878 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
3880 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4352 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4402 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4449 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
4549 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 139 MachineInstr *emitScalarToVector(unsigned EltSize,
3813 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3982 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4555 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4557 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4820 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4863 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4902 const MachineInstr *ScalarToVector = emitScalarToVector( in selectUSMovFromExtend()
4975 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
5148 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 138 MachineInstr *emitScalarToVector(unsigned EltSize,
3749 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3914 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4480 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4482 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4745 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4835 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
4964 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 138 MachineInstr *emitScalarToVector(unsigned EltSize,
3749 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3914 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4480 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4482 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4745 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4835 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
4964 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 127 MachineInstr *emitScalarToVector(unsigned EltSize,
3577 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3743 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4294 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4296 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4624 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4674 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4721 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
4840 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 138 MachineInstr *emitScalarToVector(unsigned EltSize,
3749 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3914 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4480 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4482 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4745 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4835 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
4964 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 138 MachineInstr *emitScalarToVector(unsigned EltSize,
3749 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3914 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4480 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4482 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4745 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4835 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
4964 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 127 MachineInstr *emitScalarToVector(unsigned EltSize,
3577 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3743 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4294 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4296 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4624 emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4674 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4721 MachineInstr *ScalarToVec = emitScalarToVector( in selectInsertElt()
4840 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 138 MachineInstr *emitScalarToVector(unsigned EltSize,
3749 MachineInstr *AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
3914 MachineInstr *ScalarToVector = emitScalarToVector( in emitExtractVectorElt()
4480 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op1, MIRBuilder); in emitVectorConcat()
4482 emitScalarToVector(ScalarTy.getSizeInBits(), DstRC, Op2, MIRBuilder); in emitVectorConcat()
4745 IndexLoad = emitScalarToVector(64, &AArch64::FPR128RegClass, in selectShuffleVector()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4835 emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); in selectInsertElt()
4964 emitScalarToVector(DstTy.getElementType().getSizeInBits(), DstRC, in selectBuildVector()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 70 bool emitScalarToVector(unsigned &Dst, const LLT DstTy,
1564 bool AArch64InstructionSelector::emitScalarToVector( in emitScalarToVector() function in AArch64InstructionSelector
1679 emitScalarToVector(DstVec, DstTy, DstRC, I.getOperand(1).getReg(), in selectBuildVector()
|