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Searched refs:getSubRegIndices (Results 1 – 25 of 79) sorted by relevance

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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
709 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
780 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
886 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1227 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1677 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
709 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
780 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
886 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1227 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1669 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
695 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
766 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
872 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1215 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1657 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
706 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
777 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
883 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1159 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1224 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1674 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
695 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
766 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
872 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1215 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1657 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
695 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
766 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
872 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1150 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1215 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1657 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
706 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
777 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
883 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1159 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1224 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1674 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
709 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
780 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
886 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1162 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1227 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1670 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp171 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
696 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
767 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
873 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1151 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1216 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1658 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp171 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
656 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
727 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
833 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1115 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1180 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1622 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1706 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
H A DRegisterBankEmitter.cpp199 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp170 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
699 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndices()
770 const auto &SubRegIndices = RegBank.getSubRegIndices(); in emitComposeSubRegIndexLaneMask()
876 auto &SubRegIndices = RegBank.getSubRegIndices(); in runMCDesc()
1156 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1221 const auto &SubRegIndices = RegBank.getSubRegIndices(); in runTargetDesc()
1705 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump()
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/utils/TableGen/
H A DCodeGenTarget.h103 const std::vector<Record*> &getSubRegIndices() const { in getSubRegIndices() function

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