/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/panfrost/ |
H A D | panfrost_gpu.c | 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler() 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler() 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler() 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler() 118 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks() 127 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks() 221 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features() 234 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); in panfrost_gpu_init_features() 236 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); in panfrost_gpu_init_features() 256 gpu_id = gpu_read(pfdev, GPU_ID); in panfrost_gpu_init_features() [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/panfrost/ |
H A D | panfrost_gpu.c | 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler() 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler() 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler() 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler() 118 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks() 127 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks() 221 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features() 234 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); in panfrost_gpu_init_features() 236 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); in panfrost_gpu_init_features() 256 gpu_id = gpu_read(pfdev, GPU_ID); in panfrost_gpu_init_features() [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/panfrost/ |
H A D | panfrost_gpu.c | 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler() 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler() 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler() 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler() 118 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks() 127 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks() 221 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features() 234 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); in panfrost_gpu_init_features() 236 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); in panfrost_gpu_init_features() 256 gpu_id = gpu_read(pfdev, GPU_ID); in panfrost_gpu_init_features() [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/etnaviv/ |
H A D | etnaviv_gpu.c | 181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs() 523 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 550 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 572 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg() 872 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs() 873 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs() 874 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs() 875 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs() 1277 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre() 1414 status = gpu_read(gpu, status_reg); in dump_mmu_fault() [all …]
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H A D | etnaviv_perfmon.c | 46 return gpu_read(gpu, domain->profile_read); in perf_reg_read() 61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read() 80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read() 86 value += gpu_read(gpu, signal->data); in pipe_reg_read() 106 return gpu_read(gpu, reg); in hi_total_cycle_read() 120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/etnaviv/ |
H A D | etnaviv_gpu.c | 181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs() 523 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 550 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 572 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg() 872 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs() 873 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs() 874 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs() 875 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs() 1277 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre() 1414 status = gpu_read(gpu, status_reg); in dump_mmu_fault() [all …]
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H A D | etnaviv_perfmon.c | 46 return gpu_read(gpu, domain->profile_read); in perf_reg_read() 61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read() 80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read() 86 value += gpu_read(gpu, signal->data); in pipe_reg_read() 106 return gpu_read(gpu, reg); in hi_total_cycle_read() 120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/etnaviv/ |
H A D | etnaviv_gpu.c | 181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs() 523 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 550 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset() 572 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg() 872 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs() 873 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs() 874 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs() 875 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs() 1277 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre() 1414 status = gpu_read(gpu, status_reg); in dump_mmu_fault() [all …]
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H A D | etnaviv_perfmon.c | 46 return gpu_read(gpu, domain->profile_read); in perf_reg_read() 61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read() 80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read() 86 value += gpu_read(gpu, signal->data); in pipe_reg_read() 106 return gpu_read(gpu, reg); in hi_total_cycle_read() 120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_gpu.c | 1000 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover() 1068 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle() 1070 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle() 1071 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle() 1114 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq() 1205 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq() 1206 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq() 1207 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq() 1209 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq() 1211 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq() [all …]
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H A D | a2xx_gpu.c | 256 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover() 264 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover() 288 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle() 303 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq() 306 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq() 310 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq() 316 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq() 326 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq() 433 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump() 446 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get() [all …]
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H A D | a6xx_gpu.c | 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle() 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle() 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle() 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle() 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle() 928 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump() 996 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq() 1033 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq() 1034 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq() 1035 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq() [all …]
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H A D | a4xx_gpu.c | 278 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init() 359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover() 367 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover() 393 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle() 407 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq() 411 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq() 561 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get() 569 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump() 587 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume() 618 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); in a4xx_get_rptr()
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H A D | a5xx_debugfs.c | 23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print() 36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print() 49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print() 64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
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H A D | a3xx_gpu.c | 360 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover() 368 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover() 394 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle() 409 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq() 463 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump() 476 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get() 483 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_gpu.c | 1000 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover() 1068 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle() 1070 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle() 1071 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle() 1114 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq() 1205 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq() 1206 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq() 1207 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq() 1209 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq() 1211 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq() [all …]
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H A D | a2xx_gpu.c | 256 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover() 264 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover() 288 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle() 303 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq() 306 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq() 310 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq() 316 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq() 326 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq() 433 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump() 446 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get() [all …]
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H A D | a6xx_gpu.c | 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle() 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle() 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle() 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle() 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle() 928 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump() 996 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq() 1033 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq() 1034 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq() 1035 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq() [all …]
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H A D | a4xx_gpu.c | 278 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init() 359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover() 367 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover() 393 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle() 407 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq() 411 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq() 561 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get() 569 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump() 587 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume() 618 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); in a4xx_get_rptr()
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H A D | a5xx_debugfs.c | 23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print() 36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print() 49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print() 64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/msm/adreno/ |
H A D | a5xx_gpu.c | 1000 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover() 1068 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle() 1070 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle() 1071 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle() 1114 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq() 1205 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq() 1206 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq() 1207 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq() 1209 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq() 1211 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq() [all …]
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H A D | a2xx_gpu.c | 256 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover() 264 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover() 288 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle() 303 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq() 306 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq() 310 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq() 316 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq() 326 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq() 433 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump() 446 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get() [all …]
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H A D | a6xx_gpu.c | 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle() 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle() 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle() 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle() 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle() 928 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump() 996 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq() 1033 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq() 1034 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq() 1035 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq() [all …]
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H A D | a4xx_gpu.c | 278 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init() 359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover() 367 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover() 393 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle() 407 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq() 411 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq() 561 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get() 569 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump() 587 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume() 618 ring->memptrs->rptr = gpu_read(gpu, REG_A4XX_CP_RB_RPTR); in a4xx_get_rptr()
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H A D | a5xx_debugfs.c | 23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print() 36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print() 49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print() 64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
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