1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5 #include "msm_gem.h"
6 #include "msm_mmu.h"
7 #include "msm_gpu_trace.h"
8 #include "a6xx_gpu.h"
9 #include "a6xx_gmu.xml.h"
10
11 #include <linux/bitfield.h>
12 #include <linux/devfreq.h>
13 #include <linux/nvmem-consumer.h>
14 #include <linux/soc/qcom/llcc-qcom.h>
15
16 #define GPU_PAS_ID 13
17
_a6xx_check_idle(struct msm_gpu * gpu)18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
19 {
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
22
23 /* Check that the GMU is idle */
24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
25 return false;
26
27 /* Check tha the CX master is idle */
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
30 return false;
31
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
34 }
35
a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
37 {
38 /* wait for CP to drain ringbuffer: */
39 if (!adreno_idle(gpu, ring))
40 return false;
41
42 if (spin_until(_a6xx_check_idle(gpu))) {
43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
44 gpu->name, __builtin_return_address(0),
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
49 return false;
50 }
51
52 return true;
53 }
54
a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring)55 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
56 {
57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
59 uint32_t wptr;
60 unsigned long flags;
61
62 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
63 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
64 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
65
66 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
67 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
68 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
69 }
70
71 spin_lock_irqsave(&ring->preempt_lock, flags);
72
73 /* Copy the shadow to the actual register */
74 ring->cur = ring->next;
75
76 /* Make sure to wrap wptr if we need to */
77 wptr = get_wptr(ring);
78
79 spin_unlock_irqrestore(&ring->preempt_lock, flags);
80
81 /* Make sure everything is posted before making a decision */
82 mb();
83
84 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
85 }
86
get_stats_counter(struct msm_ringbuffer * ring,u32 counter,u64 iova)87 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
88 u64 iova)
89 {
90 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
91 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
92 CP_REG_TO_MEM_0_CNT(2) |
93 CP_REG_TO_MEM_0_64B);
94 OUT_RING(ring, lower_32_bits(iova));
95 OUT_RING(ring, upper_32_bits(iova));
96 }
97
a6xx_set_pagetable(struct a6xx_gpu * a6xx_gpu,struct msm_ringbuffer * ring,struct msm_file_private * ctx)98 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
99 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
100 {
101 phys_addr_t ttbr;
102 u32 asid;
103 u64 memptr = rbmemptr(ring, ttbr0);
104
105 if (ctx == a6xx_gpu->cur_ctx)
106 return;
107
108 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
109 return;
110
111 /* Execute the table update */
112 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
113 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
114
115 OUT_RING(ring,
116 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
117 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
118 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
119 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
120
121 /*
122 * Write the new TTBR0 to the memstore. This is good for debugging.
123 */
124 OUT_PKT7(ring, CP_MEM_WRITE, 4);
125 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
126 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
127 OUT_RING(ring, lower_32_bits(ttbr));
128 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
129
130 /*
131 * And finally, trigger a uche flush to be sure there isn't anything
132 * lingering in that part of the GPU
133 */
134
135 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
136 OUT_RING(ring, 0x31);
137
138 a6xx_gpu->cur_ctx = ctx;
139 }
140
a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)141 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
142 {
143 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
144 struct msm_drm_private *priv = gpu->dev->dev_private;
145 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
146 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
147 struct msm_ringbuffer *ring = submit->ring;
148 unsigned int i;
149
150 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
151
152 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
153 rbmemptr_stats(ring, index, cpcycles_start));
154
155 /*
156 * For PM4 the GMU register offsets are calculated from the base of the
157 * GPU registers so we need to add 0x1a800 to the register value on A630
158 * to get the right value from PM4.
159 */
160 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
161 rbmemptr_stats(ring, index, alwayson_start));
162
163 /* Invalidate CCU depth and color */
164 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
165 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
166
167 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
168 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
169
170 /* Submit the commands */
171 for (i = 0; i < submit->nr_cmds; i++) {
172 switch (submit->cmd[i].type) {
173 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
174 break;
175 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
176 if (priv->lastctx == submit->queue->ctx)
177 break;
178 fallthrough;
179 case MSM_SUBMIT_CMD_BUF:
180 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
181 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
182 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
183 OUT_RING(ring, submit->cmd[i].size);
184 break;
185 }
186 }
187
188 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
189 rbmemptr_stats(ring, index, cpcycles_end));
190 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
191 rbmemptr_stats(ring, index, alwayson_end));
192
193 /* Write the fence to the scratch register */
194 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
195 OUT_RING(ring, submit->seqno);
196
197 /*
198 * Execute a CACHE_FLUSH_TS event. This will ensure that the
199 * timestamp is written to the memory and then triggers the interrupt
200 */
201 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
202 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
203 CP_EVENT_WRITE_0_IRQ);
204 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
205 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
206 OUT_RING(ring, submit->seqno);
207
208 trace_msm_gpu_submit_flush(submit,
209 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
210 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
211
212 a6xx_flush(gpu, ring);
213 }
214
215 const struct adreno_reglist a630_hwcg[] = {
216 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
217 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
218 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
219 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
221 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
222 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
223 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
224 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
225 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
226 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
227 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
228 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
229 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
230 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
231 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
232 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
233 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
234 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
235 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
237 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
238 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
239 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
241 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
242 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
243 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
245 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
246 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
247 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
248 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
249 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
250 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
251 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
252 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
253 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
254 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
255 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
256 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
257 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
258 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
259 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
260 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
261 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
262 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
263 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
264 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
265 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
266 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
267 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
269 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
270 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
271 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
273 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
274 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
275 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
277 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
278 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
279 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
280 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
281 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
282 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
283 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
284 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
285 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
286 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
287 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
288 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
289 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
291 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
292 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
293 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
295 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
296 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
297 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
299 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
300 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
301 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
302 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
303 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
304 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
305 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
306 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
307 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
308 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
309 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
310 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
311 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
312 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
313 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
314 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
315 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
316 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
317 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
318 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
319 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
320 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
321 {},
322 };
323
324 const struct adreno_reglist a640_hwcg[] = {
325 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
326 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
327 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
328 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
329 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
330 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
331 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
332 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
333 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
334 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
335 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
336 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
337 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
338 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
339 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
340 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
341 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
342 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
343 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
344 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
345 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
346 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
347 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
348 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
349 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
350 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
351 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
352 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
353 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
354 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
355 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
356 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
357 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
358 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
359 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
360 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
361 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
362 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
363 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
364 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
365 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
366 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
367 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
368 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
369 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
370 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
371 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
372 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
373 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
374 {},
375 };
376
377 const struct adreno_reglist a650_hwcg[] = {
378 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
379 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
380 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
381 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
382 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
383 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
384 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
385 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
386 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
387 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
388 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
389 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
390 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
391 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
392 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
393 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
394 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
395 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
396 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
397 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
398 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
399 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
400 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
401 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
402 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
403 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
404 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
405 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
406 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
407 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
408 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
409 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
410 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
411 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
412 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
413 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
414 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
415 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
416 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
417 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
418 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
419 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
420 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
421 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
422 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
423 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
424 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
425 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
426 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
427 {},
428 };
429
a6xx_set_hwcg(struct msm_gpu * gpu,bool state)430 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
431 {
432 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
433 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
434 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
435 const struct adreno_reglist *reg;
436 unsigned int i;
437 u32 val, clock_cntl_on;
438
439 if (!adreno_gpu->info->hwcg)
440 return;
441
442 if (adreno_is_a630(adreno_gpu))
443 clock_cntl_on = 0x8aa8aa02;
444 else
445 clock_cntl_on = 0x8aa8aa82;
446
447 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
448
449 /* Don't re-program the registers if they are already correct */
450 if ((!state && !val) || (state && (val == clock_cntl_on)))
451 return;
452
453 /* Disable SP clock before programming HWCG registers */
454 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
455
456 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
457 gpu_write(gpu, reg->offset, state ? reg->value : 0);
458
459 /* Enable SP clock */
460 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
461
462 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
463 }
464
a6xx_set_ubwc_config(struct msm_gpu * gpu)465 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
466 {
467 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
468 u32 lower_bit = 2;
469 u32 amsbc = 0;
470 u32 rgb565_predicator = 0;
471 u32 uavflagprd_inv = 0;
472
473 /* a618 is using the hw default values */
474 if (adreno_is_a618(adreno_gpu))
475 return;
476
477 if (adreno_is_a640(adreno_gpu))
478 amsbc = 1;
479
480 if (adreno_is_a650(adreno_gpu)) {
481 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
482 lower_bit = 3;
483 amsbc = 1;
484 rgb565_predicator = 1;
485 uavflagprd_inv = 2;
486 }
487
488 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
489 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
490 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
491 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
492 uavflagprd_inv >> 4 | lower_bit << 1);
493 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
494 }
495
a6xx_cp_init(struct msm_gpu * gpu)496 static int a6xx_cp_init(struct msm_gpu *gpu)
497 {
498 struct msm_ringbuffer *ring = gpu->rb[0];
499
500 OUT_PKT7(ring, CP_ME_INIT, 8);
501
502 OUT_RING(ring, 0x0000002f);
503
504 /* Enable multiple hardware contexts */
505 OUT_RING(ring, 0x00000003);
506
507 /* Enable error detection */
508 OUT_RING(ring, 0x20000000);
509
510 /* Don't enable header dump */
511 OUT_RING(ring, 0x00000000);
512 OUT_RING(ring, 0x00000000);
513
514 /* No workarounds enabled */
515 OUT_RING(ring, 0x00000000);
516
517 /* Pad rest of the cmds with 0's */
518 OUT_RING(ring, 0x00000000);
519 OUT_RING(ring, 0x00000000);
520
521 a6xx_flush(gpu, ring);
522 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
523 }
524
525 /*
526 * Check that the microcode version is new enough to include several key
527 * security fixes. Return true if the ucode is safe.
528 */
a6xx_ucode_check_version(struct a6xx_gpu * a6xx_gpu,struct drm_gem_object * obj)529 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
530 struct drm_gem_object *obj)
531 {
532 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
533 struct msm_gpu *gpu = &adreno_gpu->base;
534 u32 *buf = msm_gem_get_vaddr(obj);
535 bool ret = false;
536
537 if (IS_ERR(buf))
538 return false;
539
540 /*
541 * Targets up to a640 (a618, a630 and a640) need to check for a
542 * microcode version that is patched to support the whereami opcode or
543 * one that is new enough to include it by default.
544 */
545 if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||
546 adreno_is_a640(adreno_gpu)) {
547 /*
548 * If the lowest nibble is 0xa that is an indication that this
549 * microcode has been patched. The actual version is in dword
550 * [3] but we only care about the patchlevel which is the lowest
551 * nibble of dword [3]
552 *
553 * Otherwise check that the firmware is greater than or equal
554 * to 1.90 which was the first version that had this fix built
555 * in
556 */
557 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
558 (buf[0] & 0xfff) >= 0x190) {
559 a6xx_gpu->has_whereami = true;
560 ret = true;
561 goto out;
562 }
563
564 DRM_DEV_ERROR(&gpu->pdev->dev,
565 "a630 SQE ucode is too old. Have version %x need at least %x\n",
566 buf[0] & 0xfff, 0x190);
567 } else {
568 /*
569 * a650 tier targets don't need whereami but still need to be
570 * equal to or newer than 0.95 for other security fixes
571 */
572 if (adreno_is_a650(adreno_gpu)) {
573 if ((buf[0] & 0xfff) >= 0x095) {
574 ret = true;
575 goto out;
576 }
577
578 DRM_DEV_ERROR(&gpu->pdev->dev,
579 "a650 SQE ucode is too old. Have version %x need at least %x\n",
580 buf[0] & 0xfff, 0x095);
581 }
582
583 /*
584 * When a660 is added those targets should return true here
585 * since those have all the critical security fixes built in
586 * from the start
587 */
588 }
589 out:
590 msm_gem_put_vaddr(obj);
591 return ret;
592 }
593
a6xx_ucode_init(struct msm_gpu * gpu)594 static int a6xx_ucode_init(struct msm_gpu *gpu)
595 {
596 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
597 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
598
599 if (!a6xx_gpu->sqe_bo) {
600 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
601 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
602
603 if (IS_ERR(a6xx_gpu->sqe_bo)) {
604 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
605
606 a6xx_gpu->sqe_bo = NULL;
607 DRM_DEV_ERROR(&gpu->pdev->dev,
608 "Could not allocate SQE ucode: %d\n", ret);
609
610 return ret;
611 }
612
613 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
614 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
615 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
616 drm_gem_object_put(a6xx_gpu->sqe_bo);
617
618 a6xx_gpu->sqe_bo = NULL;
619 return -EPERM;
620 }
621 }
622
623 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
624 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
625
626 return 0;
627 }
628
a6xx_zap_shader_init(struct msm_gpu * gpu)629 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
630 {
631 static bool loaded;
632 int ret;
633
634 if (loaded)
635 return 0;
636
637 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
638
639 loaded = !ret;
640 return ret;
641 }
642
643 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
644 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
645 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
646 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
647 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
648 A6XX_RBBM_INT_0_MASK_CP_RB | \
649 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
650 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
651 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
652 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
653 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
654
a6xx_hw_init(struct msm_gpu * gpu)655 static int a6xx_hw_init(struct msm_gpu *gpu)
656 {
657 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
658 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
659 int ret;
660
661 /* Make sure the GMU keeps the GPU on while we set it up */
662 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
663
664 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
665
666 /*
667 * Disable the trusted memory range - we don't actually supported secure
668 * memory rendering at this point in time and we don't want to block off
669 * part of the virtual memory space.
670 */
671 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
672 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
673 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
674
675 /* Turn on 64 bit addressing for all blocks */
676 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
677 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
678 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
679 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
680 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
681 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
682 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
683 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
684 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
685 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
686 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
687 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
688
689 /* enable hardware clockgating */
690 a6xx_set_hwcg(gpu, true);
691
692 /* VBIF/GBIF start*/
693 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
694 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
695 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
696 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
697 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
698 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
699 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
700 } else {
701 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
702 }
703
704 if (adreno_is_a630(adreno_gpu))
705 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
706
707 /* Make all blocks contribute to the GPU BUSY perf counter */
708 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
709
710 /* Disable L2 bypass in the UCHE */
711 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
712 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
713 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
714 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
715 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
716 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
717
718 if (!adreno_is_a650(adreno_gpu)) {
719 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
720 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
721 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
722
723 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
724 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
725 0x00100000 + adreno_gpu->gmem - 1);
726 }
727
728 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
729 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
730
731 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
732 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
733 else
734 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
735 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
736
737 /* Setting the mem pool size */
738 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
739
740 /* Setting the primFifo thresholds default values */
741 if (adreno_is_a650(adreno_gpu))
742 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
743 else if (adreno_is_a640(adreno_gpu))
744 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
745 else
746 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
747
748 /* Set the AHB default slave response to "ERROR" */
749 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
750
751 /* Turn on performance counters */
752 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
753
754 /* Select CP0 to always count cycles */
755 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
756
757 a6xx_set_ubwc_config(gpu);
758
759 /* Enable fault detection */
760 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
761 (1 << 30) | 0x1fffff);
762
763 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
764
765 /* Set weights for bicubic filtering */
766 if (adreno_is_a650(adreno_gpu)) {
767 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
768 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
769 0x3fe05ff4);
770 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
771 0x3fa0ebee);
772 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
773 0x3f5193ed);
774 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
775 0x3f0243f0);
776 }
777
778 /* Protect registers from the CP */
779 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
780
781 gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
782 A6XX_PROTECT_RDONLY(0x600, 0x51));
783 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
784 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
785 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
786 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
787 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
788 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
789 gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
790 A6XX_PROTECT_RDONLY(0xfc00, 0x3));
791 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
792 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
793 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
794 gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
795 A6XX_PROTECT_RDONLY(0x0, 0x4f9));
796 gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
797 A6XX_PROTECT_RDONLY(0x501, 0xa));
798 gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
799 A6XX_PROTECT_RDONLY(0x511, 0x44));
800 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
801 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
802 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
803 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
804 gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
805 A6XX_PROTECT_RW(0xbe20, 0x11f3));
806 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
807 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
808 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
809 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
810 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
811 gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
812 A6XX_PROTECT_RDONLY(0x980, 0x4));
813 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
814
815 /* Enable expanded apriv for targets that support it */
816 if (gpu->hw_apriv) {
817 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
818 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
819 }
820
821 /* Enable interrupts */
822 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
823
824 ret = adreno_hw_init(gpu);
825 if (ret)
826 goto out;
827
828 ret = a6xx_ucode_init(gpu);
829 if (ret)
830 goto out;
831
832 /* Set the ringbuffer address */
833 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
834 gpu->rb[0]->iova);
835
836 /* Targets that support extended APRIV can use the RPTR shadow from
837 * hardware but all the other ones need to disable the feature. Targets
838 * that support the WHERE_AM_I opcode can use that instead
839 */
840 if (adreno_gpu->base.hw_apriv)
841 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
842 else
843 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
844 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
845
846 /*
847 * Expanded APRIV and targets that support WHERE_AM_I both need a
848 * privileged buffer to store the RPTR shadow
849 */
850
851 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
852 if (!a6xx_gpu->shadow_bo) {
853 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
854 sizeof(u32) * gpu->nr_rings,
855 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
856 gpu->aspace, &a6xx_gpu->shadow_bo,
857 &a6xx_gpu->shadow_iova);
858
859 if (IS_ERR(a6xx_gpu->shadow))
860 return PTR_ERR(a6xx_gpu->shadow);
861 }
862
863 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
864 REG_A6XX_CP_RB_RPTR_ADDR_HI,
865 shadowptr(a6xx_gpu, gpu->rb[0]));
866 }
867
868 /* Always come up on rb 0 */
869 a6xx_gpu->cur_ring = gpu->rb[0];
870
871 a6xx_gpu->cur_ctx = NULL;
872
873 /* Enable the SQE_to start the CP engine */
874 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
875
876 ret = a6xx_cp_init(gpu);
877 if (ret)
878 goto out;
879
880 /*
881 * Try to load a zap shader into the secure world. If successful
882 * we can use the CP to switch out of secure mode. If not then we
883 * have no resource but to try to switch ourselves out manually. If we
884 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
885 * be blocked and a permissions violation will soon follow.
886 */
887 ret = a6xx_zap_shader_init(gpu);
888 if (!ret) {
889 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
890 OUT_RING(gpu->rb[0], 0x00000000);
891
892 a6xx_flush(gpu, gpu->rb[0]);
893 if (!a6xx_idle(gpu, gpu->rb[0]))
894 return -EINVAL;
895 } else if (ret == -ENODEV) {
896 /*
897 * This device does not use zap shader (but print a warning
898 * just in case someone got their dt wrong.. hopefully they
899 * have a debug UART to realize the error of their ways...
900 * if you mess this up you are about to crash horribly)
901 */
902 dev_warn_once(gpu->dev->dev,
903 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
904 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
905 ret = 0;
906 } else {
907 return ret;
908 }
909
910 out:
911 /*
912 * Tell the GMU that we are done touching the GPU and it can start power
913 * management
914 */
915 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
916
917 if (a6xx_gpu->gmu.legacy) {
918 /* Take the GMU out of its special boot mode */
919 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
920 }
921
922 return ret;
923 }
924
a6xx_dump(struct msm_gpu * gpu)925 static void a6xx_dump(struct msm_gpu *gpu)
926 {
927 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
928 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
929 adreno_dump(gpu);
930 }
931
932 #define VBIF_RESET_ACK_TIMEOUT 100
933 #define VBIF_RESET_ACK_MASK 0x00f0
934
a6xx_recover(struct msm_gpu * gpu)935 static void a6xx_recover(struct msm_gpu *gpu)
936 {
937 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
938 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
939 int i;
940
941 adreno_dump_info(gpu);
942
943 for (i = 0; i < 8; i++)
944 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
945 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
946
947 if (hang_debug)
948 a6xx_dump(gpu);
949
950 /*
951 * Turn off keep alive that might have been enabled by the hang
952 * interrupt
953 */
954 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
955
956 gpu->funcs->pm_suspend(gpu);
957 gpu->funcs->pm_resume(gpu);
958
959 msm_gpu_hw_init(gpu);
960 }
961
a6xx_fault_handler(void * arg,unsigned long iova,int flags)962 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
963 {
964 struct msm_gpu *gpu = arg;
965
966 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
967 iova, flags,
968 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
969 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
970 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
971 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
972
973 return -EFAULT;
974 }
975
a6xx_cp_hw_err_irq(struct msm_gpu * gpu)976 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
977 {
978 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
979
980 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
981 u32 val;
982
983 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
984 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
985 dev_err_ratelimited(&gpu->pdev->dev,
986 "CP | opcode error | possible opcode=0x%8.8X\n",
987 val);
988 }
989
990 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
991 dev_err_ratelimited(&gpu->pdev->dev,
992 "CP ucode error interrupt\n");
993
994 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
995 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
996 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
997
998 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
999 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1000
1001 dev_err_ratelimited(&gpu->pdev->dev,
1002 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1003 val & (1 << 20) ? "READ" : "WRITE",
1004 (val & 0x3ffff), val);
1005 }
1006
1007 if (status & A6XX_CP_INT_CP_AHB_ERROR)
1008 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1009
1010 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1011 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1012
1013 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1014 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1015
1016 }
1017
a6xx_fault_detect_irq(struct msm_gpu * gpu)1018 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1019 {
1020 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1021 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1022 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1023
1024 /*
1025 * Force the GPU to stay on until after we finish
1026 * collecting information
1027 */
1028 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1029
1030 DRM_DEV_ERROR(&gpu->pdev->dev,
1031 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1032 ring ? ring->id : -1, ring ? ring->seqno : 0,
1033 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1034 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1035 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1036 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1037 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1038 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1039 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1040
1041 /* Turn off the hangcheck timer to keep it from bothering us */
1042 del_timer(&gpu->hangcheck_timer);
1043
1044 kthread_queue_work(gpu->worker, &gpu->recover_work);
1045 }
1046
a6xx_irq(struct msm_gpu * gpu)1047 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1048 {
1049 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1050
1051 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1052
1053 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1054 a6xx_fault_detect_irq(gpu);
1055
1056 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1057 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1058
1059 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1060 a6xx_cp_hw_err_irq(gpu);
1061
1062 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1063 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1064
1065 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1066 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1067
1068 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1069 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1070
1071 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1072 msm_gpu_retire(gpu);
1073
1074 return IRQ_HANDLED;
1075 }
1076
a6xx_llc_rmw(struct a6xx_gpu * a6xx_gpu,u32 reg,u32 mask,u32 or)1077 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
1078 {
1079 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
1080 }
1081
a6xx_llc_write(struct a6xx_gpu * a6xx_gpu,u32 reg,u32 value)1082 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
1083 {
1084 return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
1085 }
1086
a6xx_llc_deactivate(struct a6xx_gpu * a6xx_gpu)1087 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1088 {
1089 llcc_slice_deactivate(a6xx_gpu->llc_slice);
1090 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1091 }
1092
a6xx_llc_activate(struct a6xx_gpu * a6xx_gpu)1093 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1094 {
1095 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1096 struct msm_gpu *gpu = &adreno_gpu->base;
1097 u32 cntl1_regval = 0;
1098
1099 if (IS_ERR(a6xx_gpu->llc_mmio))
1100 return;
1101
1102 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1103 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1104
1105 gpu_scid &= 0x1f;
1106 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1107 (gpu_scid << 15) | (gpu_scid << 20);
1108 }
1109
1110 /*
1111 * For targets with a MMU500, activate the slice but don't program the
1112 * register. The XBL will take care of that.
1113 */
1114 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1115 if (!a6xx_gpu->have_mmu500) {
1116 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1117
1118 gpuhtw_scid &= 0x1f;
1119 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1120 }
1121 }
1122
1123 if (cntl1_regval) {
1124 /*
1125 * Program the slice IDs for the various GPU blocks and GPU MMU
1126 * pagetables
1127 */
1128 if (a6xx_gpu->have_mmu500)
1129 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0),
1130 cntl1_regval);
1131 else {
1132 a6xx_llc_write(a6xx_gpu,
1133 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1134
1135 /*
1136 * Program cacheability overrides to not allocate cache
1137 * lines on a write miss
1138 */
1139 a6xx_llc_rmw(a6xx_gpu,
1140 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1141 }
1142 }
1143 }
1144
a6xx_llc_slices_destroy(struct a6xx_gpu * a6xx_gpu)1145 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1146 {
1147 llcc_slice_putd(a6xx_gpu->llc_slice);
1148 llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1149 }
1150
a6xx_llc_slices_init(struct platform_device * pdev,struct a6xx_gpu * a6xx_gpu)1151 static void a6xx_llc_slices_init(struct platform_device *pdev,
1152 struct a6xx_gpu *a6xx_gpu)
1153 {
1154 struct device_node *phandle;
1155
1156 /*
1157 * There is a different programming path for targets with an mmu500
1158 * attached, so detect if that is the case
1159 */
1160 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1161 a6xx_gpu->have_mmu500 = (phandle &&
1162 of_device_is_compatible(phandle, "arm,mmu-500"));
1163 of_node_put(phandle);
1164
1165 if (a6xx_gpu->have_mmu500)
1166 a6xx_gpu->llc_mmio = NULL;
1167 else
1168 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
1169
1170 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1171 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1172
1173 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1174 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1175 }
1176
a6xx_pm_resume(struct msm_gpu * gpu)1177 static int a6xx_pm_resume(struct msm_gpu *gpu)
1178 {
1179 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1180 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1181 int ret;
1182
1183 gpu->needs_hw_init = true;
1184
1185 trace_msm_gpu_resume(0);
1186
1187 ret = a6xx_gmu_resume(a6xx_gpu);
1188 if (ret)
1189 return ret;
1190
1191 msm_gpu_resume_devfreq(gpu);
1192
1193 a6xx_llc_activate(a6xx_gpu);
1194
1195 return 0;
1196 }
1197
a6xx_pm_suspend(struct msm_gpu * gpu)1198 static int a6xx_pm_suspend(struct msm_gpu *gpu)
1199 {
1200 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1201 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1202 int i, ret;
1203
1204 trace_msm_gpu_suspend(0);
1205
1206 a6xx_llc_deactivate(a6xx_gpu);
1207
1208 devfreq_suspend_device(gpu->devfreq.devfreq);
1209
1210 ret = a6xx_gmu_stop(a6xx_gpu);
1211 if (ret)
1212 return ret;
1213
1214 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1215 for (i = 0; i < gpu->nr_rings; i++)
1216 a6xx_gpu->shadow[i] = 0;
1217
1218 return 0;
1219 }
1220
a6xx_get_timestamp(struct msm_gpu * gpu,uint64_t * value)1221 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1222 {
1223 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1224 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1225 static DEFINE_MUTEX(perfcounter_oob);
1226
1227 mutex_lock(&perfcounter_oob);
1228
1229 /* Force the GPU power on so we can read this register */
1230 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1231
1232 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1233 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1234
1235 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1236 mutex_unlock(&perfcounter_oob);
1237 return 0;
1238 }
1239
a6xx_active_ring(struct msm_gpu * gpu)1240 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1241 {
1242 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1243 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1244
1245 return a6xx_gpu->cur_ring;
1246 }
1247
a6xx_destroy(struct msm_gpu * gpu)1248 static void a6xx_destroy(struct msm_gpu *gpu)
1249 {
1250 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1251 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1252
1253 if (a6xx_gpu->sqe_bo) {
1254 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1255 drm_gem_object_put(a6xx_gpu->sqe_bo);
1256 }
1257
1258 if (a6xx_gpu->shadow_bo) {
1259 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1260 drm_gem_object_put(a6xx_gpu->shadow_bo);
1261 }
1262
1263 a6xx_llc_slices_destroy(a6xx_gpu);
1264
1265 a6xx_gmu_remove(a6xx_gpu);
1266
1267 adreno_gpu_cleanup(adreno_gpu);
1268
1269 if (a6xx_gpu->opp_table)
1270 dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
1271
1272 kfree(a6xx_gpu);
1273 }
1274
a6xx_gpu_busy(struct msm_gpu * gpu)1275 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
1276 {
1277 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1278 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1279 u64 busy_cycles, busy_time;
1280
1281
1282 /* Only read the gpu busy if the hardware is already active */
1283 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1284 return 0;
1285
1286 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1287 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1288 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1289
1290 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1291 do_div(busy_time, 192);
1292
1293 gpu->devfreq.busy_cycles = busy_cycles;
1294
1295 pm_runtime_put(a6xx_gpu->gmu.dev);
1296
1297 if (WARN_ON(busy_time > ~0LU))
1298 return ~0LU;
1299
1300 return (unsigned long)busy_time;
1301 }
1302
1303 static struct msm_gem_address_space *
a6xx_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev)1304 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
1305 {
1306 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1307 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1308 struct iommu_domain *iommu;
1309 struct msm_mmu *mmu;
1310 struct msm_gem_address_space *aspace;
1311 u64 start, size;
1312
1313 iommu = iommu_domain_alloc(&platform_bus_type);
1314 if (!iommu)
1315 return NULL;
1316
1317 /*
1318 * This allows GPU to set the bus attributes required to use system
1319 * cache on behalf of the iommu page table walker.
1320 */
1321 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1322 adreno_set_llc_attributes(iommu);
1323
1324 mmu = msm_iommu_new(&pdev->dev, iommu);
1325 if (IS_ERR(mmu)) {
1326 iommu_domain_free(iommu);
1327 return ERR_CAST(mmu);
1328 }
1329
1330 /*
1331 * Use the aperture start or SZ_16M, whichever is greater. This will
1332 * ensure that we align with the allocated pagetable range while still
1333 * allowing room in the lower 32 bits for GMEM and whatnot
1334 */
1335 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
1336 size = iommu->geometry.aperture_end - start + 1;
1337
1338 aspace = msm_gem_address_space_create(mmu, "gpu",
1339 start & GENMASK_ULL(48, 0), size);
1340
1341 if (IS_ERR(aspace) && !IS_ERR(mmu))
1342 mmu->funcs->destroy(mmu);
1343
1344 return aspace;
1345 }
1346
1347 static struct msm_gem_address_space *
a6xx_create_private_address_space(struct msm_gpu * gpu)1348 a6xx_create_private_address_space(struct msm_gpu *gpu)
1349 {
1350 struct msm_mmu *mmu;
1351
1352 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1353
1354 if (IS_ERR(mmu))
1355 return ERR_CAST(mmu);
1356
1357 return msm_gem_address_space_create(mmu,
1358 "gpu", 0x100000000ULL, 0x1ffffffffULL);
1359 }
1360
a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)1361 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1362 {
1363 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1364 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1365
1366 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1367 return a6xx_gpu->shadow[ring->id];
1368
1369 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1370 }
1371
a618_get_speed_bin(u32 fuse)1372 static u32 a618_get_speed_bin(u32 fuse)
1373 {
1374 if (fuse == 0)
1375 return 0;
1376 else if (fuse == 169)
1377 return 1;
1378 else if (fuse == 174)
1379 return 2;
1380
1381 return UINT_MAX;
1382 }
1383
fuse_to_supp_hw(struct device * dev,u32 revn,u32 fuse)1384 static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse)
1385 {
1386 u32 val = UINT_MAX;
1387
1388 if (revn == 618)
1389 val = a618_get_speed_bin(fuse);
1390
1391 if (val == UINT_MAX) {
1392 DRM_DEV_ERROR(dev,
1393 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
1394 fuse);
1395 return UINT_MAX;
1396 }
1397
1398 return (1 << val);
1399 }
1400
a6xx_set_supported_hw(struct device * dev,struct a6xx_gpu * a6xx_gpu,u32 revn)1401 static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
1402 u32 revn)
1403 {
1404 struct opp_table *opp_table;
1405 u32 supp_hw = UINT_MAX;
1406 u16 speedbin;
1407 int ret;
1408
1409 ret = nvmem_cell_read_u16(dev, "speed_bin", &speedbin);
1410 /*
1411 * -ENOENT means that the platform doesn't support speedbin which is
1412 * fine
1413 */
1414 if (ret == -ENOENT) {
1415 return 0;
1416 } else if (ret) {
1417 DRM_DEV_ERROR(dev,
1418 "failed to read speed-bin (%d). Some OPPs may not be supported by hardware",
1419 ret);
1420 goto done;
1421 }
1422 speedbin = le16_to_cpu(speedbin);
1423
1424 supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
1425
1426 done:
1427 opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1428 if (IS_ERR(opp_table))
1429 return PTR_ERR(opp_table);
1430
1431 a6xx_gpu->opp_table = opp_table;
1432 return 0;
1433 }
1434
1435 static const struct adreno_gpu_funcs funcs = {
1436 .base = {
1437 .get_param = adreno_get_param,
1438 .hw_init = a6xx_hw_init,
1439 .pm_suspend = a6xx_pm_suspend,
1440 .pm_resume = a6xx_pm_resume,
1441 .recover = a6xx_recover,
1442 .submit = a6xx_submit,
1443 .active_ring = a6xx_active_ring,
1444 .irq = a6xx_irq,
1445 .destroy = a6xx_destroy,
1446 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1447 .show = a6xx_show,
1448 #endif
1449 .gpu_busy = a6xx_gpu_busy,
1450 .gpu_get_freq = a6xx_gmu_get_freq,
1451 .gpu_set_freq = a6xx_gmu_set_freq,
1452 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1453 .gpu_state_get = a6xx_gpu_state_get,
1454 .gpu_state_put = a6xx_gpu_state_put,
1455 #endif
1456 .create_address_space = a6xx_create_address_space,
1457 .create_private_address_space = a6xx_create_private_address_space,
1458 .get_rptr = a6xx_get_rptr,
1459 },
1460 .get_timestamp = a6xx_get_timestamp,
1461 };
1462
a6xx_gpu_init(struct drm_device * dev)1463 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1464 {
1465 struct msm_drm_private *priv = dev->dev_private;
1466 struct platform_device *pdev = priv->gpu_pdev;
1467 struct adreno_platform_config *config = pdev->dev.platform_data;
1468 const struct adreno_info *info;
1469 struct device_node *node;
1470 struct a6xx_gpu *a6xx_gpu;
1471 struct adreno_gpu *adreno_gpu;
1472 struct msm_gpu *gpu;
1473 int ret;
1474
1475 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1476 if (!a6xx_gpu)
1477 return ERR_PTR(-ENOMEM);
1478
1479 adreno_gpu = &a6xx_gpu->base;
1480 gpu = &adreno_gpu->base;
1481
1482 adreno_gpu->registers = NULL;
1483
1484 /*
1485 * We need to know the platform type before calling into adreno_gpu_init
1486 * so that the hw_apriv flag can be correctly set. Snoop into the info
1487 * and grab the revision number
1488 */
1489 info = adreno_info(config->rev);
1490
1491 if (info && info->revn == 650)
1492 adreno_gpu->base.hw_apriv = true;
1493
1494 a6xx_llc_slices_init(pdev, a6xx_gpu);
1495
1496 ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn);
1497 if (ret) {
1498 a6xx_destroy(&(a6xx_gpu->base.base));
1499 return ERR_PTR(ret);
1500 }
1501
1502 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1503 if (ret) {
1504 a6xx_destroy(&(a6xx_gpu->base.base));
1505 return ERR_PTR(ret);
1506 }
1507
1508 /* Check if there is a GMU phandle and set it up */
1509 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1510
1511 /* FIXME: How do we gracefully handle this? */
1512 BUG_ON(!node);
1513
1514 ret = a6xx_gmu_init(a6xx_gpu, node);
1515 if (ret) {
1516 a6xx_destroy(&(a6xx_gpu->base.base));
1517 return ERR_PTR(ret);
1518 }
1519
1520 if (gpu->aspace)
1521 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1522 a6xx_fault_handler);
1523
1524 return gpu;
1525 }
1526