/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
H A D | axi_mux8.v | 16 input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready, port 34 .i0_tdata(i0_tdata), .i0_tlast(i0_tlast), .i0_tvalid(i0_tvalid), .i0_tready(i0_tready), 43 .i0_tdata(i4_tdata), .i0_tlast(i4_tlast), .i0_tvalid(i4_tvalid), .i0_tready(i4_tready), 52 ….i0_tdata(o_tdata_int0), .i0_tlast(o_tlast_int0), .i0_tvalid(o_tvalid_int0), .i0_tready(o_tready_i…
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H A D | axi_mux4.v | 15 input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready, port 90 assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
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H A D | axi_filter_mux4.v | 21 input [WIDTH-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready, port 128 assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
H A D | chdr_xxxx_to_16sc_chain.v | 43 wire [63:0] i0_tdata; wire i0_tlast, i0_tvalid, i0_tready; net 56 assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready}; 96 .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready), 103 .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
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H A D | chdr_16sc_to_xxxx_chain.v | 42 wire [63:0] i0_tdata; wire i0_tlast, i0_tvalid, i0_tready; net 55 assign {o0_tdata, o0_tlast, o0_tvalid, i0_tready} = {i0_tdata, i0_tlast, i0_tvalid, o0_tready}; 94 .o0_tdata(i0_tdata), .o0_tlast(i0_tlast), .o0_tvalid(i0_tvalid), .o0_tready(i0_tready), 101 .i0_tdata(o0_tdata), .i0_tlast(o0_tlast), .i0_tvalid(o0_tvalid), .i0_tready(o0_tready),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
H A D | addsub.v | 12 input [WIDTH*2-1:0] i0_tdata, input i0_tlast, input i0_tvalid, output i0_tready, port 22 assign i0_tready = int_tvalid & int_tready;
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H A D | axi_pipe_join.v | 13 input i0_tlast, input i0_tvalid, output i0_tready, port 26 .i_tlast(i0_tlast), .i_tvalid(i0_tvalid), .i_tready(i0_tready),
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H A D | addsub.vhd | 19 i0_tready : out std_ulogic; port 86 i0_tready <= int_tvalid and int_tready;
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H A D | mult.v | 52 .i0_tlast(a_tlast), .i0_tvalid(a_tvalid), .i0_tready(a_tready),
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H A D | multiply.v | 45 .i0_tlast(a_tlast), .i0_tvalid(a_tvalid), .i0_tready(a_tready),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/ |
H A D | rfnoc_block_addsub.v | 293 .i0_tready (m_in_a_payload_tready), 317 .i0_tready (m_in_a_payload_tready),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/arm_deframer/ |
H A D | arm_deframer_tb.sv | 55 …,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/ |
H A D | pcie_wb_reg_core.v | 118 …_msgi_tdata), .i0_tlast(1'b1), .i0_tvalid(wb_msgi_tvalid & ~wb_in_rr), .i0_tready(wb_msgi_tready_i…
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H A D | pcie_iop2_msg_arbiter.v | 64 ….i0_tdata(e0_rego_tdata), .i0_tlast(e0_rego_tvalid), .i0_tvalid(e0_rego_tvalid), .i0_tready(e0_reg…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/ |
H A D | b200_core.v | 129 ….i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp… 258 ….i0_tdata(r0_rx_tdata), .i0_tlast(r0_rx_tlast), .i0_tvalid(r0_rx_tvalid), .i0_tready(r0_rx_tready),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/ |
H A D | radio_legacy.v | 471 …data_r), .i0_tlast(rx_postfc_tlast_r), .i0_tvalid(rx_postfc_tvalid_r), .i0_tready(rx_postfc_tready… 482 ….i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txre…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/ |
H A D | b205_core.v | 115 ….i0_tdata(r0_resp_tdata), .i0_tlast(r0_resp_tlast), .i0_tvalid(r0_resp_tvalid), .i0_tready(r0_resp…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/ |
H A D | arm_to_sfp_tb.sv | 248 …,c2e_tdata_int}), .i0_tlast(c2e_tlast_int), .i0_tvalid(c2e_tvalid_int), .i0_tready(c2e_tready_int),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_pcie_int.v | 294 …gt,0)}), .i0_tlast(dmatx_tlast_gt[0]), .i0_tvalid(dmatx_tvalid_gt[0]), .i0_tready(dmatx_tready_gt[…
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H A D | bus_int.v | 669 …i0_tuser,zpui0_tdata}), .i0_tlast(zpui0_tlast), .i0_tvalid(zpui0_tvalid), .i0_tready(zpui0_tready),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
H A D | axi_dma_fifo.v | 316 .i0_tdata(i_tdata), .i0_tlast(i_tlast), .i0_tvalid(i_tvalid), .i0_tready(i_tready_int),
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