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Searched refs:i1_tvalid (Results 1 – 21 of 21) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/
H A Daxi_mux8.v17 input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready, port
35 .i1_tdata(i1_tdata), .i1_tlast(i1_tlast), .i1_tvalid(i1_tvalid), .i1_tready(i1_tready),
44 .i1_tdata(i5_tdata), .i1_tlast(i5_tlast), .i1_tvalid(i5_tvalid), .i1_tready(i5_tready),
53 ….i1_tdata(o_tdata_int1), .i1_tlast(o_tlast_int1), .i1_tvalid(o_tvalid_int1), .i1_tready(o_tready_i…
H A Daxi_mux4.v16 input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready, port
39 else if(i1_tvalid)
50 else if(i1_tvalid)
92 assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
H A Daxi_filter_mux4.v22 input [WIDTH-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready, port
55 else if(i1_tvalid) begin
72 else if(i1_tvalid) begin
130 assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/
H A Dchdr_xxxx_to_16sc_chain.v44 wire [63:0] i1_tdata; wire i1_tlast, i1_tvalid, i1_tready; net
67 .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
97 .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
104 .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
H A Dchdr_16sc_to_xxxx_chain.v43 wire [63:0] i1_tdata; wire i1_tlast, i1_tvalid, i1_tready; net
66 .i_tdata(i1_tdata), .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
95 .o1_tdata(i1_tdata), .o1_tlast(i1_tlast), .o1_tvalid(i1_tvalid), .o1_tready(i1_tready),
102 .i1_tdata(o1_tdata), .i1_tlast(o1_tlast), .i1_tvalid(o1_tvalid), .i1_tready(o1_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/
H A Daddsub.v13 input [WIDTH*2-1:0] i1_tdata, input i1_tlast, input i1_tvalid, output i1_tready, port
21 assign int_tvalid = i0_tvalid & i1_tvalid;
H A Daxi_pipe_join.v14 input i1_tlast, input i1_tvalid, output i1_tready, port
32 .i_tlast(i1_tlast), .i_tvalid(i1_tvalid), .i_tready(i1_tready),
H A Daddsub.vhd23 i1_tvalid : in std_ulogic; port
107 int_tvalid <= i0_tvalid and i1_tvalid;
H A Dmult.v53 .i1_tlast(b_tlast), .i1_tvalid(b_tvalid), .i1_tready(b_tready),
H A Dmultiply.v46 .i1_tlast(b_tlast), .i1_tvalid(b_tvalid), .i1_tready(b_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/
H A Drfnoc_block_addsub.v296 .i1_tvalid (m_in_b_payload_tvalid),
320 .i1_tvalid (m_in_b_payload_tvalid),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/arm_deframer/
H A Darm_deframer_tb.sv56 .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/
H A Dpcie_wb_reg_core.v119 ….i1_tdata(pcie_out_auto_resp_data), .i1_tlast(1'b1), .i1_tvalid(pcie_out_auto_resp_valid), .i1_tre…
H A Dpcie_iop2_msg_arbiter.v65 ….i1_tdata(e1_rego_tdata), .i1_tlast(e1_rego_tvalid), .i1_tvalid(e1_rego_tvalid), .i1_tready(e1_reg…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/
H A Db200_core.v130 ….i1_tdata(r1_resp_tdata), .i1_tlast(r1_resp_tlast), .i1_tvalid(r1_resp_tvalid), .i1_tready(r1_resp…
259 ….i1_tdata(r1_rx_tdata), .i1_tlast(r1_rx_tlast), .i1_tvalid(r1_rx_tvalid), .i1_tready(r1_rx_tready),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/radio_200/
H A Dradio_legacy.v472 ….i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_e…
483 ….i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tread…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/
H A Db205_core.v116 ….i1_tdata(l0_resp_tdata), .i1_tlast(l0_resp_tlast), .i1_tvalid(l0_resp_tvalid), .i1_tready(l0_resp…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/arm_to_sfp_loopback/
H A Darm_to_sfp_tb.sv249 .i1_tdata(), .i1_tlast(), .i1_tvalid(), .i1_tready(),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_pcie_int.v295 ….i1_tdata({3'd1, `GET_DMA_BUS(dmatx_tdata_gt,1)}), .i1_tlast(dmatx_tlast_gt[1]), .i1_tvalid(dmatx_…
H A Dbus_int.v670 ….i1_tdata({zpui1_tuser,zpui1_tdata}), .i1_tlast(zpui1_tlast), .i1_tvalid(zpui1_tvalid), .i1_tready…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/
H A Daxi_dma_fifo.v317 ….i1_tdata(i_tdata_bist), .i1_tlast(i_tlast_bist), .i1_tvalid(i_tvalid_bist), .i1_tready(i_tready_b…