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/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/risc_cpu/
H A Dpic.h41 sc_in<bool> ireq1; // interrupt request 1 member
56 sensitive << ireq0 << ireq1 << ireq2 << ireq3 ; in SC_CTOR()
H A Dpic.cpp47 } else if (ireq1.read() == true) { in entry()
H A Dmain.cpp216 sc_signal<bool> ireq1("IREQ1") ; in sc_main() local
362 APIC << ireq0 << ireq1 << ireq2 << ireq3 <<intack_cpu << rd_wr in sc_main()