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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_const_opt_red.v66 logic match1_o; register
117 .match1_o ( match1_o ),
176 if (match1_o != match2_o) begin
177 $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o);
269 output logic match1_o, port
275 match1_o = 1'b0;
286 match1_o = 1'b1;