1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2020 Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t(/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 integer cyc = 0; 14 reg [63:0] crc; 15 reg [63:0] sum; 16 17 // Take CRC data and apply to testblock inputs 18 wire [31:0] in = crc[31:0]; 19 20 /*AUTOWIRE*/ 21 // Beginning of automatic wires (for undeclared instantiated-module outputs) 22 logic a1; // From test of Test.v 23 logic a10; // From test of Test.v 24 logic a11; // From test of Test.v 25 logic a2; // From test of Test.v 26 logic a3; // From test of Test.v 27 logic a4; // From test of Test.v 28 logic a5; // From test of Test.v 29 logic a6; // From test of Test.v 30 logic a7; // From test of Test.v 31 logic a8; // From test of Test.v 32 logic a9; // From test of Test.v 33 logic o1; // From test of Test.v 34 logic o10; // From test of Test.v 35 logic o11; // From test of Test.v 36 logic o2; // From test of Test.v 37 logic o3; // From test of Test.v 38 logic o4; // From test of Test.v 39 logic o5; // From test of Test.v 40 logic o6; // From test of Test.v 41 logic o7; // From test of Test.v 42 logic o8; // From test of Test.v 43 logic o9; // From test of Test.v 44 logic x1; // From test of Test.v 45 logic x2; // From test of Test.v 46 logic x3; // From test of Test.v 47 logic x4; // From test of Test.v 48 logic x5; // From test of Test.v 49 logic x6; // From test of Test.v 50 logic x7; // From test of Test.v 51 logic x8; // From test of Test.v 52 logic x9; // From test of Test.v 53 logic z1; // From test of Test.v 54 logic z2; // From test of Test.v 55 logic z3; // From test of Test.v 56 logic z4; // From test of Test.v 57 logic z5; // From test of Test.v 58 logic z6; // From test of Test.v 59 logic z7; // From test of Test.v 60 // End of automatics 61 62 wire [15:0] vec_i = crc[15:0]; 63 wire [31:0] i = crc[31:0]; 64 logic b8_i; 65 logic b12_i; 66 logic match1_o; 67 logic match2_o; 68 69 Test test(/*AUTOINST*/ 70 // Outputs 71 .a1 (a1), 72 .a2 (a2), 73 .a3 (a3), 74 .a4 (a4), 75 .a5 (a5), 76 .a6 (a6), 77 .a7 (a7), 78 .a8 (a8), 79 .a9 (a9), 80 .a10 (a10), 81 .a11 (a11), 82 .o1 (o1), 83 .o2 (o2), 84 .o3 (o3), 85 .o4 (o4), 86 .o5 (o5), 87 .o6 (o6), 88 .o7 (o7), 89 .o8 (o8), 90 .o9 (o9), 91 .o10 (o10), 92 .o11 (o11), 93 .x1 (x1), 94 .x2 (x2), 95 .x3 (x3), 96 .x4 (x4), 97 .x5 (x5), 98 .x6 (x6), 99 .x7 (x7), 100 .x8 (x8), 101 .x9 (x9), 102 .z1 (z1), 103 .z2 (z2), 104 .z3 (z3), 105 .z4 (z4), 106 .z5 (z5), 107 .z6 (z6), 108 .z7 (z7), 109 // Inputs 110 .clk (clk), 111 .i (i[31:0])); 112 113 match i_match( 114 .vec_i ( i[15:0] ), 115 .b8_i ( b8_i ), 116 .b12_i ( b12_i ), 117 .match1_o ( match1_o ), 118 .match2_o ( match2_o ) 119 ); 120 121 122 // Aggregate outputs into a single result vector 123 // verilator lint_off WIDTH 124 wire [63:0] result = {a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11, 125 o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11, 126 x1,x2,x3,x4,x5,x6,x7,x8,x9}; 127 // verilator lint_on WIDTH 128 129 // Test loop 130 always @ (posedge clk) begin 131`ifdef TEST_VERBOSE 132 $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); 133 $display("a %b %b %b %b %b %b %b %b %b %b %b", a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11); 134 $display("o %b %b %b %b %b %b %b %b %b %b %b", o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11); 135 $display("x %b %b %b %b %b %b %b %b %b", x1, x2, x3, x4, x5, x6, x7, x8, x9); 136`endif 137 cyc <= cyc + 1; 138 crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; 139 sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; 140 if (cyc == 0) begin 141 // Setup 142 crc <= 64'h5aef0c8d_d70a4497; 143 sum <= '0; 144 b8_i <= 1'b0; 145 b12_i <= 1'b0; 146 end 147 else if (cyc < 10) begin 148 sum <= '0; 149 end 150 else if (cyc < 99) begin 151 if (a1 != a2) $stop; 152 if (a1 != a3) $stop; 153 if (a1 != a4) $stop; 154 if (a1 != a5) $stop; 155 if (a6 != a7) $stop; 156 if (a8 != a9) $stop; 157 if (o1 != o2) $stop; 158 if (o1 != o3) $stop; 159 if (o1 != o4) $stop; 160 if (o1 != o5) $stop; 161 if (o6 != o7) $stop; 162 if (o8 != o9) $stop; 163 if (x1 != x2) $stop; 164 if (x1 != x3) $stop; 165 if (x1 != x4) $stop; 166 if (x1 != x5) $stop; 167 if (x1 != x6) $stop; 168 if (x1 != x7) $stop; 169 if (z1 != '0) $stop; 170 if (z2 != '1) $stop; 171 if (z3 != '0) $stop; 172 if (z4 != '0) $stop; 173 if (z5 != '1) $stop; 174 if (z6 != '1) $stop; 175 if (z7 != '0) $stop; 176 if (match1_o != match2_o) begin 177 $write("[%0t] cyc==%0d m1=%d != m2=%d\n", $time, cyc, match1_o, match2_o); 178 $stop; 179 end 180 end 181 else begin 182 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); 183 if (crc !== 64'hc77bb9b3784ea091) $stop; 184 // What checksum will we end up with (above print should match) 185`define EXPECTED_SUM 64'h727fb78d09c1981e 186 if (sum !== `EXPECTED_SUM) $stop; 187 $write("*-* All Finished *-*\n"); 188 $finish; 189 end 190 end 191 192endmodule 193 194module Test(/*AUTOARG*/ 195 // Outputs 196 a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, o1, o2, o3, o4, o5, 197 o6, o7, o8, o9, o10, o11, x1, x2, x3, x4, x5, x6, x7, x8, x9, z1, 198 z2, z3, z4, z5, z6, z7, 199 // Inputs 200 clk, i 201 ); 202 203 input clk; 204 input [31:0] i; 205 206 output logic a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11; 207 output logic o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11; 208 output logic x1, x2, x3, x4, x5, x6, x7, x8, x9; 209 output logic z1, z2, z3, z4, z5, z6, z7; 210 211 logic [127:0] d; 212 logic [17:0] e; 213 always_ff @(posedge clk) d <= {i, ~i, ~i, i}; 214 always_ff @(posedge clk) e <= i[17:00]; 215 216 always_ff @(posedge clk) begin 217 a1 <= (i[5] & ~i[3] & i[1]); 218 a2 <= (i[5]==1 & i[3]==0 & i[1]==1); 219 a3 <= &{i[5], ~i[3], i[1]}; 220 a4 <= ((i & 32'b101010) == 32'b100010); 221 a5 <= ((i & 32'b001010) == 32'b000010) & i[5]; 222 a6 <= &i[5:3]; 223 a7 <= i[5] & i[4] & i[3] & i[5] & i[4]; 224 a8 <= &(~i[5:3]); 225 a9 <= ~i[5] & !i[4] & !i[3] && ~i[5] && !i[4]; 226 a10 <= ~(i[5] & ~d[3]) & (!i[5] & d[1]); // cannot be optimized 227 a11 <= d[0] & d[33] & d[66] & d[99] & !d[31] & !d[62] & !d[93] & !d[124] & e[0] & !e[1] & e[2]; 228 // 229 o1 <= (~i[5] | i[3] | ~i[1]); 230 o2 <= (i[5]!=1 | i[3]!=0 | i[1]!=1); 231 o3 <= |{~i[5], i[3], ~i[1]}; 232 o4 <= ((i & 32'b101010) != 32'b100010); 233 o5 <= ((i & 32'b001010) != 32'b000010) | !i[5]; 234 o6 <= |i[5:3]; 235 o7 <= i[5] | i[4] | i[3] | i[5] | i[4]; 236 o8 <= |(~i[5:3]); 237 o9 <= ~i[5] | !i[4] | ~i[3] || !i[5] || ~i[4]; 238 o10 <= ~(~i[5] | d[3]) | (i[5] | ~d[1]); // cannot be optimized 239 o11 <= d[0] | d[33] | d[66] | d[99] | !d[31] | !d[62] | !d[93] | !d[124] | e[0] | !e[1] | e[2]; 240 // 241 x1 <= (i[5] ^ ~i[3] ^ i[1]); 242 x2 <= (i[5]==1 ^ i[3]==0 ^ i[1]==1); 243 x3 <= ^{i[5], ~i[3], i[1]}; 244 x4 <= ^((i & 32'b101010) ^ 32'b001000); 245 x5 <= ^((i & 32'b001010) ^ 32'b001000) ^ i[5]; 246 x6 <= i[5] ^ ~i[3] ^ i[1] ^ i[3] ^ !i[1] ^ i[3] ^ ~i[1]; 247 x7 <= i[5] ^ (^((i & 32'b001010) ^ 32'b001000)); 248 x8 <= ~(~i[5] ^ d[3]) ^ (i[5] ^ ~d[1]); 249 x9 <= d[0] ^ d[33] ^ d[66] ^ d[99] ^ !d[31] ^ !d[62] ^ !d[93] ^ !d[124] ^ e[0] ^ !e[1] ^ e[2]; 250 // 251 // All zero/all one cases 252 z1 <= (i[5] & ~i[3] & ~i[5]); 253 z2 <= (~i[5] | i[3] | i[5]); 254 z3 <= (i[5] ^ ~i[3] ^ ~i[5] ^ i[3]); 255 z4 <= &(i[0] && !i[0]); 256 z5 <= |(i[1] || !i[1]); 257 z6 <= ^(i[2] ^ !i[2]); 258 z7 <= ^(i[2] ^ i[2]); 259 end 260 261endmodule 262 263 264module match 265 ( 266 input logic [15:0] vec_i, 267 input logic b8_i, 268 input logic b12_i, 269 output logic match1_o, 270 output logic match2_o 271 ); 272 273 always_comb 274 begin 275 match1_o = 1'b0; 276 if ( 277 (vec_i[1:0] == 2'b0) 278 && 279 (vec_i[4] == 1'b0) 280 && 281 (vec_i[8] == b8_i) 282 && 283 (vec_i[12] == b12_i) 284 ) 285 begin 286 match1_o = 1'b1; 287 end 288 end 289 290 always_comb 291 begin 292 match2_o = 1'b0; 293 if ( 294 (vec_i[1:0] == 2'b0) 295 && 296 (vec_i[8] == b8_i) 297 && 298 (vec_i[12] == b12_i) 299 && 300 (vec_i[4] == 1'b0) 301 ) 302 begin 303 match2_o = 1'b1; 304 end 305 end 306 307endmodule 308