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Searched refs:meas_clk (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_clocking.v44 output meas_clk, port
142 .meas_clk (meas_clk),
H A Dmb_clocks.xdc65 create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v742 wire meas_clk; net
841 .meas_clk(meas_clk),
3752 .MeasClk(meas_clk), //in std_logic
3865 .MeasClk(meas_clk), //in std_logic
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Dn3xx.v729 wire meas_clk; net
830 .meas_clk(meas_clk),
3726 .MeasClk(meas_clk), //in std_logic
3837 .MeasClk(meas_clk), //in std_logic