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Searched refs:meas_clk_reset (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn3xx_core.v46 output reg meas_clk_reset, port
480 meas_clk_reset <= 1'b0;
511 meas_clk_reset <= cp_glob_req_data[12];
568 cp_glob_resp_data[12] <= meas_clk_reset;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v744 wire meas_clk_reset; net
843 .misc_clks_reset(meas_clk_reset),
3545 .meas_clk_reset(meas_clk_reset),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Dn3xx.v731 wire meas_clk_reset; net
832 .misc_clks_reset(meas_clk_reset),
3475 .meas_clk_reset(meas_clk_reset),