mmVGA_CACHE_CONTROL (reference) in projects: dports

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Searched refs:mmVGA_CACHE_CONTROL (Results 1 – 25 of 36) sorted by relevance

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dce/
H A D	dce_6_0_d.h	`4378 #define mmVGA_CACHE_CONTROL 0x00CB macro`
H A D	dce_8_0_d.h	`5143 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_0_d.h	`6103 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_10_0_d.h	`6026 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_2_d.h	`7777 #define mmVGA_CACHE_CONTROL 0xcb macro`
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dce/
H A D	dce_6_0_d.h	`4378 #define mmVGA_CACHE_CONTROL 0x00CB macro`
H A D	dce_8_0_d.h	`5143 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_10_0_d.h	`6026 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_0_d.h	`6103 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_2_d.h	`7777 #define mmVGA_CACHE_CONTROL 0xcb macro`
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dce/
H A D	dce_6_0_d.h	`4378 #define mmVGA_CACHE_CONTROL 0x00CB macro`
H A D	dce_8_0_d.h	`5143 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_0_d.h	`6103 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_10_0_d.h	`6026 #define mmVGA_CACHE_CONTROL 0xcb macro`
H A D	dce_11_2_d.h	`7777 #define mmVGA_CACHE_CONTROL 0xcb macro`
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A D	dcn_3_0_1_offset.h	`166 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_1_0_offset.h	`406 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_2_1_0_offset.h	`110 #define mmVGA_CACHE_CONTROL … macro`
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A D	dcn_3_0_1_offset.h	`166 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_2_1_0_offset.h	`110 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_1_0_offset.h	`406 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_3_0_2_offset.h	`50 #define mmVGA_CACHE_CONTROL … macro`
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A D	dcn_3_0_1_offset.h	`166 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_2_1_0_offset.h	`110 #define mmVGA_CACHE_CONTROL … macro`
H A D	dcn_1_0_offset.h	`406 #define mmVGA_CACHE_CONTROL … macro`