| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_mux4.v | 22 wire o_tlast_int, o_tvalid_int, o_tready_int; net
47 if(o_tready_int & o_tvalid_int & o_tlast_int)
60 if(o_tready_int & o_tvalid_int & o_tlast_int)
71 if(o_tready_int & o_tvalid_int & o_tlast_int)
80 if(o_tready_int & o_tvalid_int & o_tlast_int)
90 assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
105 assign o_tready_int = o_tready;
110 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_filter_mux4.v | 28 wire o_tlast_int, o_tvalid_int, o_tready_int; net
69 if(o_tready_int & o_tvalid_int & o_tlast_int)
90 if(o_tready_int & o_tvalid_int & o_tlast_int)
106 if(o_tready_int & o_tvalid_int & o_tlast_int)
118 if(o_tready_int & o_tvalid_int & o_tlast_int)
128 assign {i3_tready, i2_tready, i1_tready, i0_tready} = mx_state & {4{o_tready_int}};
143 assign o_tready_int = o_tready | filter_packet;
148 assign o_tready_int = o_tready_int_fifo | filter_packet;
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| H A D | axi_mux.v | 25 wire o_tlast_int, o_tvalid_int, o_tready_int; net
57 if(o_tlast_int & o_tvalid_int & o_tready_int)
79 assign i_tready_int[i] = st_active & o_tready_int & (st_port == i);
100 assign o_tready_int = o_tready;
105 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_mux_select.v | 28 wire o_tlast_int, o_tvalid_int, o_tready_int; net
71 assign end_of_packet = o_tlast_int & o_tvalid_int & o_tready_int;
108 assign i_tready_int = (1'b1 << select_hold) & {SIZE{o_tready_int}};
115 assign o_tready_int = o_tready;
119 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_fifo_32_64_tb.v | 61 wire o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int; net
86 …), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
98 assign o_tready_int = o_tready_int2;
112 if(o_tvalid_int & o_tready_int)
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| H A D | axi_demux.v | 53 wire [SIZE-1:0] o_tlast_int, o_tready_int, o_tvalid_int; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | axi_setting_reg.v | 44 wire o_tready_int; net
55 if (o_tvalid_int & o_tready_int) begin
73 if (~o_tready_int) begin
86 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
93 assign o_tready_int = o_tready;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
| H A D | new_rx_framer.v | 42 wire o_tlast_int, o_tvalid_int, o_tready_int; net
162 if(o_tlast_int & o_tvalid_int & o_tready_int)
224 if(o_tvalid_int && o_tready_int)
227 if(o_tvalid_int && o_tready_int)
230 if(o_tvalid_int && o_tready_int && o_tlast_int)
245 assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
248 assign dfifo_tready = (outstate == OUT_BODY) ? o_tready_int : 1'b0;
252 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/ |
| H A D | axi_fifo_32_64_tb.v | 63 wire o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int; net
88 …), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
100 assign o_tready_int = o_tready_int2;
114 if(o_tvalid_int & o_tready_int)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_packet_gate/ |
| H A D | axi_packet_gate_tb.v | 89 wire o_tlast_int, o_tready_int, o_tvalid_int; net
101 …_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
105 … .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | chdr_fifo_large.v | 48 wire o_tlast_int, o_tvalid_int, o_tready_int; net
53 .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
58 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
| H A D | chdr_ingress_fifo.v | 49 wire o_tlast_int, o_tvalid_int, o_tready_int; net
54 .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
59 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_fifo.v | 303 wire o_tvalid_int, o_tready_int, o_tlast_int; net
356 .o_tdata(o_tdata_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int)
365 .s_axis_tvalid(o_tvalid_int), .s_axis_tready(o_tready_int),
373 end else if (o_tlast_int & o_tvalid_int & o_tready_int) begin
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ |
| H A D | b200.edf | 23360 …r_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/o_tready_int") (joined
26065 …gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int") (joined
37504 …er_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/o_tready_int") (joined
44192 …_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/o_tready_int") (joined
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.data/cache/ |
| H A D | b200_ngc_d1c0f267.edif | 35848 …_rx_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_rx/buffer_whole_pkt/o_tready_int")
37651 …p_buffer_whole_pkt_o_tready_int "slave_fifo32/fifo64_to_gpmc32_resp/buffer_whole_pkt/o_tready_int")
44050 …x_checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_tx/checker/gate_xfer/o_tready_int")
48962 …checker_gate_xfer_o_tready_int "slave_fifo32/fifo64_to_gpmc32_ctrl/checker/gate_xfer/o_tready_int")
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