| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | axi_setting_reg.v | 43 reg o_tlast_int, o_tvalid_int = VALID_AT_RESET; register
49 o_tvalid_int <= VALID_AT_RESET;
55 if (o_tvalid_int & o_tready_int) begin
58 o_tvalid_int <= 1'b0;
67 o_tvalid_int <= 1'b1;
86 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
92 assign o_tvalid = o_tvalid_int;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_mux4.v | 22 wire o_tlast_int, o_tvalid_int, o_tready_int; net
47 if(o_tready_int & o_tvalid_int & o_tlast_int)
60 if(o_tready_int & o_tvalid_int & o_tlast_int)
71 if(o_tready_int & o_tvalid_int & o_tlast_int)
80 if(o_tready_int & o_tvalid_int & o_tlast_int)
92 assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
104 assign o_tvalid = o_tvalid_int;
110 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_filter_mux4.v | 28 wire o_tlast_int, o_tvalid_int, o_tready_int; net
69 if(o_tready_int & o_tvalid_int & o_tlast_int)
90 if(o_tready_int & o_tvalid_int & o_tlast_int)
106 if(o_tready_int & o_tvalid_int & o_tlast_int)
118 if(o_tready_int & o_tvalid_int & o_tlast_int)
130 assign o_tvalid_int = |(mx_state & ({i3_tvalid, i2_tvalid, i1_tvalid, i0_tvalid}));
142 assign o_tvalid = o_tvalid_int & !filter_packet;
152 ….i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int & !filter_packet), .i_tready(o_tready_…
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| H A D | axi_mux_select.v | 28 wire o_tlast_int, o_tvalid_int, o_tready_int; net
68 assign in_packet = in_packet_reg || o_tvalid_int;
71 assign end_of_packet = o_tlast_int & o_tvalid_int & o_tready_int;
88 end else if (o_tvalid_int) begin
107 assign o_tvalid_int = i_tvalid_int[select_hold];
114 assign o_tvalid = o_tvalid_int;
119 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_mux.v | 25 wire o_tlast_int, o_tvalid_int, o_tready_int; net
57 if(o_tlast_int & o_tvalid_int & o_tready_int)
83 assign o_tvalid_int = st_active & i_tvalid_int[st_port];
99 assign o_tvalid = o_tvalid_int;
105 .i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| H A D | axi_fifo_32_64_tb.v | 61 wire o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int; net
86 ….o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_t…
97 assign o_tvalid_int2 = o_tvalid_int;
112 if(o_tvalid_int & o_tready_int)
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| H A D | axi_demux.v | 53 wire [SIZE-1:0] o_tlast_int, o_tready_int, o_tvalid_int; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/vita_200/ |
| H A D | new_rx_framer.v | 42 wire o_tlast_int, o_tvalid_int, o_tready_int; net
162 if(o_tlast_int & o_tvalid_int & o_tready_int)
224 if(o_tvalid_int && o_tready_int)
227 if(o_tvalid_int && o_tready_int)
230 if(o_tvalid_int && o_tready_int && o_tlast_int)
242 assign o_tvalid_int = (outstate != OUT_IDLE) & dfifo_tvalid;
245 assign hfifo_tready = o_tvalid_int && o_tready_int && o_tlast_int;
252 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_fifo_32_64/ |
| H A D | axi_fifo_32_64_tb.v | 63 wire o_tlast, o_tlast_int, o_tvalid, o_tvalid_int, o_tready, o_tready_int; net
88 ….o_tdata(o_tdata_int), .o_tuser(o_tuser_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_t…
99 assign o_tvalid_int2 = o_tvalid_int;
114 if(o_tvalid_int & o_tready_int)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_packet_gate/ |
| H A D | axi_packet_gate_tb.v | 89 wire o_tlast_int, o_tready_int, o_tvalid_int; net
101 ….o_tdata({o_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_t…
105 … .i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | chdr_fifo_large.v | 48 wire o_tlast_int, o_tvalid_int, o_tready_int; net
53 .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
58 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
| H A D | chdr_ingress_fifo.v | 49 wire o_tlast_int, o_tvalid_int, o_tready_int; net
54 .o_tdata({o_tlast_int, o_tdata_int}), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int),
59 .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_fifo.v | 303 wire o_tvalid_int, o_tready_int, o_tlast_int; net
356 .o_tdata(o_tdata_int), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int)
365 .s_axis_tvalid(o_tvalid_int), .s_axis_tready(o_tready_int),
373 end else if (o_tlast_int & o_tvalid_int & o_tready_int) begin
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