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Searched refs:op_divu (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/mess/mame-mame0226/src/devices/cpu/
H A Ddrcbex64.h174 void op_divu(Assembler &a, const uml::instruction &inst);
H A Ddrcbex86.h175 void op_divu(Assembler &a, const uml::instruction &inst);
H A Ddrcbex64.cpp360 { uml::OP_DIVU, &drcbe_x64::op_divu }, // DIVU dst,edst,src1,src2[,f]
3263 void drcbe_x64::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x64
H A Ddrcbex86.cpp238 { uml::OP_DIVU, &drcbe_x86::op_divu }, // DIVU dst,edst,src1,src2[,f]
4163 void drcbe_x86::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x86
/dports/emulators/mame/mame-mame0226/src/devices/cpu/
H A Ddrcbex64.h174 void op_divu(Assembler &a, const uml::instruction &inst);
H A Ddrcbex86.h175 void op_divu(Assembler &a, const uml::instruction &inst);
H A Ddrcbex64.cpp360 { uml::OP_DIVU, &drcbe_x64::op_divu }, // DIVU dst,edst,src1,src2[,f]
3263 void drcbe_x64::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x64
H A Ddrcbex86.cpp238 { uml::OP_DIVU, &drcbe_x86::op_divu }, // DIVU dst,edst,src1,src2[,f]
4163 void drcbe_x86::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x86
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/
H A Dlm32_allprofiles.v7095 wire op_divu; net
7247 assign op_divu = instruction[ 31:26] == 6'b100011;
7328 assign divide = op_divu;
20032 wire op_divu; net
20184 assign op_divu = instruction[ 31:26] == 6'b100011;
20265 assign divide = op_divu;
96543 wire op_divu; net
96695 assign op_divu = instruction[ 31:26] == 6'b100011;
96776 assign divide = op_divu;