Searched refs:op_divu (Results 1 – 9 of 9) sorted by relevance
/dports/emulators/mess/mame-mame0226/src/devices/cpu/ |
H A D | drcbex64.h | 174 void op_divu(Assembler &a, const uml::instruction &inst);
|
H A D | drcbex86.h | 175 void op_divu(Assembler &a, const uml::instruction &inst);
|
H A D | drcbex64.cpp | 360 { uml::OP_DIVU, &drcbe_x64::op_divu }, // DIVU dst,edst,src1,src2[,f] 3263 void drcbe_x64::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x64
|
H A D | drcbex86.cpp | 238 { uml::OP_DIVU, &drcbe_x86::op_divu }, // DIVU dst,edst,src1,src2[,f] 4163 void drcbe_x86::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x86
|
/dports/emulators/mame/mame-mame0226/src/devices/cpu/ |
H A D | drcbex64.h | 174 void op_divu(Assembler &a, const uml::instruction &inst);
|
H A D | drcbex86.h | 175 void op_divu(Assembler &a, const uml::instruction &inst);
|
H A D | drcbex64.cpp | 360 { uml::OP_DIVU, &drcbe_x64::op_divu }, // DIVU dst,edst,src1,src2[,f] 3263 void drcbe_x64::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x64
|
H A D | drcbex86.cpp | 238 { uml::OP_DIVU, &drcbe_x86::op_divu }, // DIVU dst,edst,src1,src2[,f] 4163 void drcbe_x86::op_divu(Assembler &a, const instruction &inst) in op_divu() function in drc::drcbe_x86
|
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/ |
H A D | lm32_allprofiles.v | 7095 wire op_divu; net 7247 assign op_divu = instruction[ 31:26] == 6'b100011; 7328 assign divide = op_divu; 20032 wire op_divu; net 20184 assign op_divu = instruction[ 31:26] == 6'b100011; 20265 assign divide = op_divu; 96543 wire op_divu; net 96695 assign op_divu = instruction[ 31:26] == 6'b100011; 96776 assign divide = op_divu;
|