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Searched refs:pciercx_cfg010 (Results 1 – 25 of 59) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/pci/
H A Dpcie-octeon.c391 union cvmx_pciercx_cfg010 pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
533 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
537 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
540 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/pci/
H A Dpcie-octeon.c391 union cvmx_pciercx_cfg010 pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
533 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
537 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
540 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/pci/
H A Dpcie-octeon.c391 union cvmx_pciercx_cfg010 pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
533 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
537 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
540 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-octeon/
H A Dcvmx-pcie.c453 cvmx_pciercx_cfg010_t pciercx_cfg010; in __cvmx_pcie_rc_initialize_config_space() local
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
461 pciercx_cfg010.s.umem_base = 0x100; in __cvmx_pcie_rc_initialize_config_space()
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32); in __cvmx_pcie_rc_initialize_config_space()

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