/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/pci/ |
H A D | pcie-octeon.c | 384 union cvmx_pciercx_cfg030 pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 404 pciercx_cfg030.s.mps = MPS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 405 pciercx_cfg030.s.mrrs = MRRS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 407 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 408 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 414 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 416 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 418 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 420 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 422 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/pci/ |
H A D | pcie-octeon.c | 384 union cvmx_pciercx_cfg030 pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 404 pciercx_cfg030.s.mps = MPS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 405 pciercx_cfg030.s.mrrs = MRRS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 407 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 408 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 414 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 416 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 418 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 420 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 422 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/pci/ |
H A D | pcie-octeon.c | 384 union cvmx_pciercx_cfg030 pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 404 pciercx_cfg030.s.mps = MPS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 405 pciercx_cfg030.s.mrrs = MRRS_CN5XXX; in __cvmx_pcie_rc_initialize_config_space() 407 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 408 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 414 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 416 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 418 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 420 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 422 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 329 cvmx_pciercx_cfg030_t pciercx_cfg030; in __cvmx_pcie_rc_initialize_config_space() local 331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_config_space() 333 pciercx_cfg030.s.mps = MPS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX; in __cvmx_pcie_rc_initialize_config_space() 339 pciercx_cfg030.s.ro_en = 1; in __cvmx_pcie_rc_initialize_config_space() 341 pciercx_cfg030.s.ns_en = 1; in __cvmx_pcie_rc_initialize_config_space() 343 pciercx_cfg030.s.ce_en = 1; in __cvmx_pcie_rc_initialize_config_space() 345 pciercx_cfg030.s.nfe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 347 pciercx_cfg030.s.fe_en = 1; in __cvmx_pcie_rc_initialize_config_space() 349 pciercx_cfg030.s.ur_en = 1; in __cvmx_pcie_rc_initialize_config_space() [all …]
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