/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; 1367 pciercx_cfg031.s.mls = 1; 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, 1435 max_gen = pciercx_cfg031.s.mls; 1437 max_width = pciercx_cfg031.s.mlw; 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; 1903 pciercx_cfg031.u32 = 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { 1917 pciercx_cfg031.s.mls = 2; [all …]
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/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/mach-octeon/ |
H A D | cvmx-pcie.c | 1364 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2() local 1367 pciercx_cfg031.s.mls = 1; in __cvmx_pcie_rc_initialize_gen2() 1404 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_link_gen2_v3() local 1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, in __cvmx_pcie_rc_initialize_link_gen2_v3() 1435 max_gen = pciercx_cfg031.s.mls; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1437 max_width = pciercx_cfg031.s.mlw; in __cvmx_pcie_rc_initialize_link_gen2_v3() 1753 cvmx_pciercx_cfg031_t pciercx_cfg031; in __cvmx_pcie_rc_initialize_gen2_v3() local 1903 pciercx_cfg031.u32 = in __cvmx_pcie_rc_initialize_gen2_v3() 1913 if (pciercx_cfg031.s.mls == 3 && result != 2) { in __cvmx_pcie_rc_initialize_gen2_v3() 1917 pciercx_cfg031.s.mls = 2; in __cvmx_pcie_rc_initialize_gen2_v3() [all …]
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