| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/pci/ |
| H A D | pcie-octeon.c | 393 union cvmx_pciercx_cfg035 pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
547 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
548 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
549 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
551 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
552 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/pci/ |
| H A D | pcie-octeon.c | 393 union cvmx_pciercx_cfg035 pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
547 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
548 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
549 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
551 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
552 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/pci/ |
| H A D | pcie-octeon.c | 393 union cvmx_pciercx_cfg035 pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
547 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
548 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
549 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
551 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
552 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-octeon/ |
| H A D | cvmx-pcie.c | 471 cvmx_pciercx_cfg035_t pciercx_cfg035; in __cvmx_pcie_rc_initialize_config_space() local
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); in __cvmx_pcie_rc_initialize_config_space()
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ in __cvmx_pcie_rc_initialize_config_space()
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32); in __cvmx_pcie_rc_initialize_config_space()
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