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Searched refs:posedge (Results 1 – 25 of 237) sorted by relevance

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/dports/devel/lattice-ice40-examples-hx1k/iCE40HX1K-EVB-69df5a7fc2daa8f00a984426b721499f6df22492/windows/ice40blinkingled/ice40blinkingled_Implmnt/sbt/outputs/simulation_netlist/
H A Dled_but_ex1_sbt_vital.sdf24 (SETUP (posedge ce) (posedge clk) (0:0:0))
26 (HOLD (posedge ce) (posedge clk) (0:0:0))
30 (HOLD (posedge in0) (posedge clk) (0:0:0))
34 (HOLD (posedge in1) (posedge clk) (0:0:0))
38 (HOLD (posedge in2) (posedge clk) (0:0:0))
42 (HOLD (posedge in3) (posedge clk) (0:0:0))
66 (SETUP (posedge ce) (posedge clk) (0:0:0))
68 (HOLD (posedge ce) (posedge clk) (0:0:0))
72 (HOLD (posedge in0) (posedge clk) (0:0:0))
76 (HOLD (posedge in1) (posedge clk) (0:0:0))
[all …]
H A Dled_but_ex1_sbt.sdf24 (SETUP (posedge ce) (posedge clk) (0:0:0))
26 (HOLD (posedge ce) (posedge clk) (0:0:0))
30 (HOLD (posedge in0) (posedge clk) (0:0:0))
34 (HOLD (posedge in1) (posedge clk) (0:0:0))
38 (HOLD (posedge in2) (posedge clk) (0:0:0))
42 (HOLD (posedge in3) (posedge clk) (0:0:0))
66 (SETUP (posedge ce) (posedge clk) (0:0:0))
68 (HOLD (posedge ce) (posedge clk) (0:0:0))
72 (HOLD (posedge in0) (posedge clk) (0:0:0))
76 (HOLD (posedge in1) (posedge clk) (0:0:0))
[all …]
/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_cdc_async_debug_bad.out5 …t_cdc_async_bad.v: output q0 SRC=@(posedge clk or neg…
6 …t_cdc_async_bad.v: output q1 SRC=@(posedge clk or neg…
7 …t_cdc_async_bad.v: output q2 SRC=@(posedge clk or neg…
13 …: wire t.__Vcellinp__flop4__rst_n SRC=@(posedge clk) DST=@(posedge clk or …
14 …: wire t.rst1_n SRC=@(posedge clk) DST=@(posedge clk or …
15 …wire t.rst2_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or …
16 …: wire t.rst4_n SRC=@(posedge clk) DST=@(posedge clk or …
17 …wire t.rst5_waive_n SRC=@(* or posedge clk) DST=@(posedge clk or …
18 …wire t.rst6_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or …
19 …wire t.rst6a_bad_n SRC=@(* or posedge clk) DST=@(posedge clk or …
[all …]
H A Dt_debug_emitv.out17 @(*)@([settle])@([initial])@(posedge clk)@(negedge
22 posedge
28 always @([settle])@([initial])@(posedge clk)@(negedge
51 always @(posedge clk)@(negedge clk) begin
52 $display("posedge clk");
54 always @(posedge clk)@(negedge clk) begin
57 always @(posedge clk)@(negedge clk) begin
200 /*verilator public_flat_rw @(posedge clk)@(negedge
202 always @(posedge clk)@(negedge clk) begin
205 always @(posedge clk)@(negedge clk) begin
H A Dt_cover_line.out48 000020 always @ (posedge clk) begin
155 000040 always @ (posedge clk) begin
181 000040 always @ (posedge clk) begin
216 000020 always @ (posedge clk) begin
246 always @ (posedge clk) begin
253 000020 always @ (posedge clk) begin
/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/examples.acc/
H A Dacc_nxtchld.plg36 $period((posedge clk):19000, (posedge clk):20000, 1200);
46 $period((posedge clk):25000, (posedge clk):26100, 1200);
48 $width((negedge clk):26000, (posedge clk):26100, 500);
55 $period((posedge clk):30100, (posedge clk):31100, 1200);
58 $width((posedge clk):31100, (negedge clk):31130, 600);
61 $period((posedge clk):31100, (posedge clk):31190, 1200);
66 hold(of setuphold)((posedge clk):31190, d:31220, 50);
73 $recovery((posedge d):31280, clk:31310, 200);
75 $period((posedge clk):31190, (posedge clk):31310, 1200);
82 $recovery((posedge d):31280, clk:31410, 200);
[all …]
H A Dpchg_fdsp.plg190 $period((posedge clk):19000, (posedge clk):20000, 1200);
225 $period((posedge clk):25000, (posedge clk):26100, 1200);
227 $width((negedge clk):26000, (posedge clk):26100, 500);
249 $period((posedge clk):30100, (posedge clk):31100, 1200);
255 $width((posedge clk):31100, (negedge clk):31130, 600);
261 $period((posedge clk):31100, (posedge clk):31190, 1200);
269 hold(of setuphold)((posedge clk):31190, d:31220, 50);
293 $recovery((posedge d):31280, clk:31310, 200);
295 $period((posedge clk):31190, (posedge clk):31310, 1200);
308 $recovery((posedge d):31280, clk:31410, 200);
[all …]
/dports/cad/yosys/yosys-yosys-0.12/tests/sat/
H A Dclk2fflogic.ys3 always @(posedge clk or posedge s) if ( s) q[ 0] <= 1'b1; else q[ 0] <= d;
4 always @(posedge clk or negedge s) if (!s) q[ 1] <= 1'b1; else q[ 1] <= d;
5 always @(posedge clk or posedge r) if ( r) q[ 2] <= 1'b0; else q[ 2] <= d;
6 always @(posedge clk or negedge r) if (!r) q[ 3] <= 1'b0; else q[ 3] <= d;
7 always @(negedge clk or posedge s) if ( s) q[ 4] <= 1'b1; else q[ 4] <= d;
9 always @(negedge clk or posedge r) if ( r) q[ 6] <= 1'b0; else q[ 6] <= d;
13 always @(posedge clk or posedge s or posedge r) if ( r) q[ 8] <= 1'b0; else if ( s) q[ 8] <= 1'b1; …
14 //always @(posedge clk or posedge s or negedge r) if (!r) q[ 9] <= 1'b0; else if ( s) q[ 9] <= 1'b1…
15 //always @(posedge clk or negedge s or posedge r) if ( r) q[10] <= 1'b0; else if (!s) q[10] <= 1'b1…
21 always @(negedge clk or posedge s or posedge r) if ( r) q[12] <= 1'b0; else if ( s) q[12] <= 1'b1; …
[all …]
/dports/cad/openroad/OpenROAD-2.0/src/dbSta/test/
H A Dexample1.sdf41 (SETUP D (posedge CK) (.5:.5:.5))
42 (HOLD D (posedge CK) (.1:.1:.1))
43 (PERIOD (posedge CK) (1.0:2.0:3.0))
55 (SETUP D (posedge CK) (.5:.5:.5))
56 (HOLD D (posedge CK) (.1:.1:.1))
57 (PERIOD (posedge CK) (1.0:2.0:3.0))
69 (SETUP D (posedge CK) (.5:.5:.5))
70 (HOLD D (posedge CK) (.1:.1:.1))
71 (PERIOD (posedge CK) (1.0:2.0:3.0))
/dports/cad/openroad/OpenROAD-2.0/src/sta/examples/
H A Dexample1.sdf41 (SETUP D (posedge CK) (.5:.5:.5))
42 (HOLD D (posedge CK) (.1:.1:.1))
43 (PERIOD (posedge CK) (1.0:2.0:3.0))
55 (SETUP D (posedge CK) (.5:.5:.5))
56 (HOLD D (posedge CK) (.1:.1:.1))
57 (PERIOD (posedge CK) (1.0:2.0:3.0))
69 (SETUP D (posedge CK) (.5:.5:.5))
70 (HOLD D (posedge CK) (.1:.1:.1))
71 (PERIOD (posedge CK) (1.0:2.0:3.0))
/dports/cad/p5-Verilog-Perl/Verilog-Perl-3.478/t/
H A D60_vpassert.out181 @ (posedge clk) ;
185 @ (posedge clk) ;
188 @ (posedge clk) ;
191 @ (posedge clk) ;
194 always @ (posedge clk) begin
272 always @ (posedge clk) if (_umessageclk2)
279 foreach_label__27: cover property (@(posedge clk) (_ucoverclk4));
281 foreach_label__26: cover property (@(posedge clk) (_ucoverclk5));
283 foreach_label__25: cover property (@(posedge clk) (_ucoverclk6));
285 foreach_label__24: cover property (@(posedge clk) (_ucoverclk7));
[all …]
/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/examples.vpi/
H A Dvdrvld1.plg226 $period((posedge clk):19000, (posedge clk):20000, 1200);
236 $period((posedge clk):25000, (posedge clk):26100, 1200);
238 $width((negedge clk):26000, (posedge clk):26100, 500);
245 $period((posedge clk):30100, (posedge clk):31100, 1200);
248 $width((posedge clk):31100, (negedge clk):31130, 600);
251 $period((posedge clk):31100, (posedge clk):31190, 1200);
256 hold(of setuphold)((posedge clk):31190, d:31220, 50);
263 $recovery((posedge d):31280, clk:31310, 200);
265 $period((posedge clk):31190, (posedge clk):31310, 1200);
272 $recovery((posedge d):31280, clk:31410, 200);
[all …]
/dports/games/linwarrior/linwarrior/source/
H A DcAlert.h56 bool posedge; variable
65 …nt shapetype, std::string message, OID group, bool positive = true, bool posedge = true, bool once…
76 this->posedge = posedge;
128 if (posedge) {
137 if (!posedge) {
/dports/cad/iverilog/verilog-11.0/vvp/examples/
H A Dedge.vvp20 ; This example tests the operation of a simple posedge event. The module
31 ; always @(posedge a) $display("Got a posedge.");
39 V_main.b .event posedge, V_main.a;
50 %vpi_call 0 0 "$display", "Got a posedge." {0 0 0};
/dports/cad/yosys/yosys-yosys-0.12/tests/opt/
H A Dopt_dff_dffmux.ys4 always @(posedge clk) if (ce) o <= i;
19 always @(posedge clk) if (ce) o <= i;
35 always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
50 always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
65 always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
81 always @(posedge clk) begin
101 always @(posedge clk) begin
H A Dopt_mem_priority.ys13 always @(posedge clk) begin
46 always @(posedge clk) begin
79 always @(posedge clk) begin
113 always @(posedge clk) begin
146 always @(posedge clk) begin
181 always @(posedge clk) begin
H A Dmemory_dff_trans.ys15 always @(posedge clk) begin
53 always @(posedge clk) begin
94 always @(posedge clk) begin
141 always @(posedge clk) begin
186 always @(posedge clk) begin
231 always @(posedge clk) begin
280 always @(posedge clk) begin
325 always @(posedge clk) begin
372 always @(posedge clk) begin
421 always @(posedge clk) begin
[all …]
/dports/cad/yosys/yosys-yosys-0.12/tests/arch/xilinx/
H A Ddsp_fastfir.ys38 always @(posedge i_clk)
40 always @(posedge i_clk)
42 always @(posedge i_clk)
51 always @(posedge i_clk)
53 always @(posedge i_clk)
55 always @(posedge i_clk)
/dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/
H A Dxfirrtl16 code_verilog_tutorial_if_else.v empty module (everything is under 'always @ (posedge clk)')
18 code_verilog_tutorial_parallel_if.v empty module (everything is under 'always @ (posedge clk)')
20 code_verilog_tutorial_simple_if.v empty module (everything is under 'always @ (posedge clk)')
21 code_verilog_tutorial_task_global.v empty module (everything is under 'always @ (posedge clk)')
/dports/cad/verilator/verilator-4.216/src/
H A DV3GraphTest.cpp183 V3GraphTestVertex* posedge = n = new V3GraphTestVertex(gp, "*posedge clk*"); in runTest() local
194 new V3GraphEdge(gp, posedge, n, 2); in runTest()
201 new V3GraphEdge(gp, posedge, n, 2); in runTest()
215 new V3GraphEdge(gp, posedge, n, 2); in runTest()
222 new V3GraphEdge(gp, posedge, n, 2); in runTest()
232 new V3GraphEdge(gp, posedge, n, 2); in runTest()
238 new V3GraphEdge(gp, posedge, n, 2); in runTest()
/dports/cad/yosys/yosys-yosys-0.12/tests/verilog/
H A Dconst_sr.ys7 always @(posedge clk, posedge nop, posedge rst) begin
/dports/cad/yosys/yosys-yosys-0.12/techlibs/ice40/tests/
H A Dtest_dsp_map.sh15 E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
16 E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
17 E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
18 E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
/dports/cad/yosys/yosys-yosys-0.12/tests/proc/
H A Dbug2656.ys7 always @(posedge clk)
11 always @(posedge clk, posedge rst)
/dports/cad/tkgate/tkgate-2.1/test/verga/
H A Dedges1.out6 6: posedge x=1
8 8: posedge x=1
H A Dedges2.out3 posedge x=1
5 posedge x=1

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