1module Vt_debug_emitv___024root; 2 input logic clk; 3 input logic in; 4 signed int [31:0] t.array[0:2]; 5 logic [15:0] t.pubflat; 6 logic [15:0] t.pubflat_r; 7 signed int [31:0] t.fd; 8 signed int [31:0] t.i; 9 signed int [31:0] t.cyc; 10 signed int [31:0] t.fo; 11 signed int [31:0] t.sum; 12 signed real t.r; 13 string t.str; 14 signed int [31:0] t._Vpast_0_0; 15 signed int [31:0] t._Vpast_1_0; 16 signed int [31:0] t.unnamedblk3.i; 17 @(*)@([settle])@([initial])@(posedge clk)@(negedge 18 clk)always @( 19 *)@( 20 [settle])@( 21 [initial])@( 22 posedge 23 clk)@( 24 negedge 25 clk) begin 26 $display("stmt"); 27 end 28 always @([settle])@([initial])@(posedge clk)@(negedge 29 clk) begin 30 $display("stmt"); 31 end 32 initial begin 33 // Function: f 34 $write("stmt\nstmt 0 99\n"); 35 // Function: t 36 $display("stmt"); 37 // Function: f 38 $write("stmt\nstmt 1 -1\n"); 39 // Function: t 40 $display("stmt"); 41 // Function: f 42 $display("stmt"); 43 $display("stmt 2 -2"); 44 // Function: t 45 $display("stmt"); 46 $display("stmt"); 47 end 48 49 ???? // CFUNC '_final_TOP' 50 $display("stmt"); 51 always @(posedge clk)@(negedge clk) begin 52 $display("posedge clk"); 53 end 54 always @(posedge clk)@(negedge clk) begin 55 __Vdly__t.pubflat_r <= t.pubflat; 56 end 57 always @(posedge clk)@(negedge clk) begin 58 __Vdly__t.cyc <= (32'sh1 + t.cyc); 59 __Vdly__t.r <= (0.01 + t.r); 60 t.fo = t.cyc; 61 // Function: inc 62 __Vtask_t.sub.inc__2__i = t.fo; 63 __Vtask_t.sub.inc__2__o = (32'h1 + __Vtask_t.sub.inc__2__i[31:1]); 64 t.sum = __Vtask_t.sub.inc__2__o; 65 // Function: f 66 __Vfunc_t.sub.f__3__v = t.sum; 67 begin : label0 68 begin : label0 69 if ((32'sh0 == __Vfunc_t.sub.f__3__v)) begin 70 __Vfunc_t.sub.f__3__Vfuncout = 32'sh21; 71 disable label0; 72 end 73 __Vfunc_t.sub.f__3__Vfuncout = (32'h1 74 + __Vfunc_t.sub.f__3__v[2]); 75 disable label0; 76 end 77 end 78 t.sum = __Vfunc_t.sub.f__3__Vfuncout; 79 $display("[%0t] sum = %~", $timet.sum, t.sum); 80 $display("a?= %d", ($c(32'sh1) ? $c(32'sh14) 81 : $c(32'sh1e))); 82 $c(;); 83 $display("%d", $c(0)); 84 $fopen(72'h2f6465762f6e756c6c); 85 $fclose(t.fd); 86 $fopen(72'h2f6465762f6e756c6c, 8'h72); 87 $fgetc(t.fd); 88 $fflush(t.fd); 89 $fscanf(t.fd, "%d", t.sum); 90 ; 91 $fdisplay(32'h69203d20, "%~", t.sum); 92 $fwrite(t.fd, "hello"); 93 $readmemh(t.fd, t.array); 94 $readmemh(t.fd, t.array, 32'sh0); 95 $readmemh(t.fd, t.array, 32'sh0, 32'sh0); 96 t.sum = 32'sh0; 97 t.unnamedblk3.i = 32'sh0; 98 begin : label0 99 while ((t.unnamedblk3.i < t.cyc)) begin 100 t.sum = (t.sum + t.unnamedblk3.i); 101 if ((32'sha < t.sum)) begin 102 disable label0; 103 end 104 else begin 105 t.sum = (32'sh1 + t.sum); 106 end 107 t.unnamedblk3.i = (32'h1 + t.unnamedblk3.i); 108 end 109 end 110 if ((32'sh63 == t.cyc)) begin 111 $finish; 112 end 113 if ((32'sh64 == t.cyc)) begin 114 $stop; 115 end 116 if (in) begin 117 $display("1"); 118 end 119 else begin 120 $display("default"); 121 end 122 if (in) begin 123 $display("1"); 124 end 125 else begin 126 $display("default"); 127 end 128 if (in) begin 129 $display("1"); 130 end 131 else begin 132 $display("default"); 133 end 134 if (in) begin 135 $display("1"); 136 end 137 else begin 138 $display("default"); 139 end 140 if (in) begin 141 $display("1"); 142 end 143 else begin 144 $display("0"); 145 end 146 priority if (in) begin 147 $display("1"); 148 end 149 else begin 150 $display("0"); 151 end 152 unique if (in) begin 153 $display("1"); 154 end 155 else begin 156 $display("0"); 157 end 158 unique0 if (in) begin 159 $display("1"); 160 end 161 else begin 162 $display("0"); 163 end 164 $display("%~%~", t._Vpast_0_0t._Vpast_1_0, 165 t._Vpast_1_0); 166 t.str = $sformatf("cyc=%~", t.cyc); 167 ; 168 $display("str = %@", t.str); 169 $display("%% [%t] [%^] to=%o td=%d", $time$realtime 170 $time$time, $realtime$time$time, $time 171 $time, $time); 172 $sscanf(40'h666f6f3d35, "foo=%d", t.i); 173 ; 174 $printtimescale; 175 if ((32'sh5 != t.i)) begin 176 $stop; 177 end 178 t.sum = 179 ???? // RAND 180 32'sha; 181 $display("%g", $log10(t.r)); 182 $display("%g", $ln(t.r)); 183 $display("%g", $exp(t.r)); 184 $display("%g", $sqrt(t.r)); 185 $display("%g", $floor(t.r)); 186 $display("%g", $ceil(t.r)); 187 $display("%g", $sin(t.r)); 188 $display("%g", $cos(t.r)); 189 $display("%g", $tan(t.r)); 190 $display("%g", $asin(t.r)); 191 $display("%g", $acos(t.r)); 192 $display("%g", $atan(t.r)); 193 $display("%g", $sinh(t.r)); 194 $display("%g", $cosh(t.r)); 195 $display("%g", $tanh(t.r)); 196 $display("%g", $asinh(t.r)); 197 $display("%g", $acosh(t.r)); 198 $display("%g", $atanh(t.r)); 199 end 200 /*verilator public_flat_rw @(posedge clk)@(negedge 201 clk) t.pubflat*/ 202 always @(posedge clk)@(negedge clk) begin 203 __Vdly__t._Vpast_0_0 <= t.cyc; 204 end 205 always @(posedge clk)@(negedge clk) begin 206 __Vdly__t._Vpast_1_0 <= t.cyc; 207 end 208 __Vdly__t._Vpast_1_0 = t._Vpast_1_0; 209 t._Vpast_1_0 = __Vdly__t._Vpast_1_0; 210 __Vdly__t._Vpast_0_0 = t._Vpast_0_0; 211 t._Vpast_0_0 = __Vdly__t._Vpast_0_0; 212 __Vdly__t.r = t.r; 213 t.r = __Vdly__t.r; 214 __Vdly__t.cyc = t.cyc; 215 t.cyc = __Vdly__t.cyc; 216 __Vdly__t.pubflat_r = t.pubflat_r; 217 t.pubflat_r = __Vdly__t.pubflat_r; 218 always @(negedge clk) begin 219 $display("negedge clk, pfr = %x", t.pubflat_r); 220 end 221 signed int [31:0] __Vtask_t.sub.inc__2__i; 222 signed int [31:0] __Vtask_t.sub.inc__2__o; 223 signed int [31:0] __Vfunc_t.sub.f__3__Vfuncout; 224 signed int [31:0] __Vfunc_t.sub.f__3__v; 225 logic [15:0] __Vdly__t.pubflat_r; 226 signed int [31:0] __Vdly__t.cyc; 227 signed real __Vdly__t.r; 228 signed int [31:0] __Vdly__t._Vpast_0_0; 229 signed int [31:0] __Vdly__t._Vpast_1_0; 230endmodule 231package Vt_debug_emitv___024unit; 232endpackage 233package Vt_debug_emitv_Pkg; 234endpackage 235class Vt_debug_emitv___024unit__03a__03aCls; 236signed int [31:0] member; 237 238???? // CFUNC '__VnoInFunc_method' 239 240???? // CFUNC 'new' 241$_CSTMT(_ctor_var_reset(vlSymsp); 242); 243$unit::Cls.member = 32'sh1; 244endclass 245/*class*/package Vt_debug_emitv___024unit__03a__03aCls__Vclpkg; 246end/*class*/package 247