Home
last modified time | relevance | path

Searched refs:radio_clk_2x (Results 1 – 11 of 11) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_cap_gen/
H A Dcat_io_lvds_dual_mode.v89 wire radio_clk_2x; // rx_clk_p divided by 2 net
121 .I1 (radio_clk_2x),
162 always @(posedge radio_clk_2x)
190 always @(posedge radio_clk_2x)
274 always @(posedge radio_clk_2x)
368 .radio_clk_2x (radio_clk_2x),
H A Dcat_io_lvds.v59 output radio_clk_2x, port
134 .radio_clk_2x (radio_clk_2x),
H A Dcat_input_lvds.v78 output radio_clk_2x, port
200 BUFG radio_clk_2x_bufg (.O(radio_clk_2x), .I(sdr_clk_2x));
203 assign radio_clk_2x = sdr_clk_2x;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dmb_timing.xdc34 create_generated_clock -name radio_clk_2x \
40 set_clock_groups -physically_exclusive -group radio_clk_1x -group radio_clk_2x
80 set RADIO_CLK_2X_PERIOD [get_property period [get_clocks radio_clk_2x]]
88 set_max_delay -from [get_pins e320_core_i/fp_gpio_src_reg_reg[*]/C] -to [get_clocks radio_clk_2x] $…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/io_cap_gen/cat_io_lvds/
H A Dcat_io_lvds_tb.v321 .radio_clk_2x (),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300.v246 wire radio_clk, radio_clk_2x, dac_dci_clk; net
383 .CLK_OUT1(radio_clk), .CLK_OUT2(radio_clk_2x), .CLK_OUT3(dac_dci_clk),
625 .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk),
638 .tx_clk_2x(radio_clk_2x), .tx_clk_1x(radio_clk), .tx_dci_clk(dac_dci_clk),
H A Dtiming.xdc59 create_generated_clock -name radio_clk_2x [get_pins -hierarchical -filter {NAME =~ "*ra…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Ddb_clocks.xdc68 create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
H A Dn3xx.v743 wire radio_clk_2x; net
3731 .SampleClk2xOut(radio_clk_2x), //out std_logic
3732 .SampleClk2x(radio_clk_2x), //in std_logic
3843 .SampleClk2x(radio_clk_2x), //in std_logic
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v755 wire radio_clk_2x; net
3757 .SampleClk2xOut(radio_clk_2x), //out std_logic
3758 .SampleClk2x(radio_clk_2x), //in std_logic
3871 .SampleClk2x(radio_clk_2x), //in std_logic
H A Ddb_timing.xdc55 create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1…