| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | ram_to_fifo.v | 37 ram_2port #(.DWIDTH(DWIDTH), .AWIDTH(AWIDTH)) ram_2port instance
|
| H A D | fft_shift.v | 63 ram_2port #(
70 ram_2port #(
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | double_buffer.v | 68 ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer0
74 ram_2port #(.DWIDTH(36),.AWIDTH(BUF_SIZE)) buffer1
|
| H A D | ram_2port.v | 20 module ram_2port module
|
| H A D | Makefile.srcs | 23 ram_2port.v \
|
| H A D | longfifo.v | 55 ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/fifo/ |
| H A D | buffer_int2.v | 169 ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here
175 ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here
|
| H A D | buffer_int_tb.v | 73 ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port instance
|
| H A D | fifo_long.v | 62 ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | axi_stream_to_wb.v | 117 ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) input_stream_bram
138 ram_2port #(.DWIDTH(64), .AWIDTH(AWIDTH-3)) output_stream_bram
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/rfnoc/axi_rate_change/ |
| H A D | Makefile | 23 $(LIB_DIR)/control/ram_2port.v \
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/ |
| H A D | cvita_dest_lookup.v | 24 ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc_200/ |
| H A D | cvita_dest_lookup_legacy.v | 24 ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/serdes/ |
| H A D | serdes_tb.v | 66 ram_2port #(.DWIDTH(32),.AWIDTH(9))
100 ram_2port #(.DWIDTH(32),.AWIDTH(9))
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | Makefile.srcs | 33 ram_2port.v \
|
| H A D | ram_2port.v | 54 module ram_2port #( module
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/custom/ |
| H A D | power_trig.v | 83 ram_2port #(.DWIDTH(32),.AWIDTH(9)) delay_line
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
| H A D | variable_delay_line.v | 130 ram_2port #(
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/gpmc/ |
| H A D | fifo_to_gpmc.v | 154 ram_2port #(.DWIDTH(18),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
|
| H A D | gpmc_to_fifo.v | 159 ram_2port #(.DWIDTH(16),.AWIDTH(PTR_WIDTH + ADDR_WIDTH)) async_fifo_bram
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo/ |
| H A D | axi_fifo_bram.v | 55 ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
|
| H A D | axi_packet_gate.v | 65 ram_2port #(
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/fifo_200/ |
| H A D | axi_fifo_legacy.v | 66 ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/map/ |
| H A D | kv_map.v | 69 ram_2port #(
|
| H A D | cam_bram.v | 136 ram_2port #(
|