/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | internals.h | 233 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 796 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 2667 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 2693 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 2706 tcr->raw_tcr = value; in vmsa_tcr_el1_write() 9002 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 9008 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 9550 t0sz = extract32(tcr->raw_tcr, 0, 6); in get_phys_addr_lpae() 9555 t0sz = extract32(tcr->raw_tcr, 0, 3); in get_phys_addr_lpae() 9574 t1sz = extract32(tcr->raw_tcr, 16, 6); in get_phys_addr_lpae() 9612 tg = extract32(tcr->raw_tcr, 14, 2); in get_phys_addr_lpae() 9624 epd = extract32(tcr->raw_tcr, 23, 1); in get_phys_addr_lpae() [all …]
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H A D | cpu.h | 163 uint64_t raw_tcr; member
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | internals.h | 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 848 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3431 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3449 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3460 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3473 tcr->raw_tcr = value; in vmsa_tcr_el1_write() 8681 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { in regime_using_lpae_format() 8912 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 8918 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 9408 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters_both() 9479 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 9654 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae()
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H A D | cpu.h | 154 uint64_t raw_tcr; member
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | internals.h | 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 848 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3431 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3449 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3460 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3473 tcr->raw_tcr = value; in vmsa_tcr_el1_write() 8681 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { in regime_using_lpae_format() 8912 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 8918 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 9408 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters_both() 9479 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 9654 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae()
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H A D | cpu.h | 154 uint64_t raw_tcr; member
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | internals.h | 273 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 783 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3926 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3944 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3955 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3968 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 4518 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in tlbbits_for_regime() 10849 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10855 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 11392 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 11461 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 11650 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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H A D | cpu.c | 212 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | internals.h | 262 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 769 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3956 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3974 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3985 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3998 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 4545 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in tlbbits_for_regime() 10501 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10507 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 11044 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 11113 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 11302 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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H A D | cpu.c | 211 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | internals.h | 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 928 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3951 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3969 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3980 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3993 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 9858 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { in regime_using_lpae_format() 10089 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10095 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 10609 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 10671 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 10834 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | internals.h | 273 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 791 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3702 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3720 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3731 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3744 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 4294 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in tlbbits_for_regime() 10587 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10593 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 11130 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 11199 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 11388 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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H A D | cpu.c | 212 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | internals.h | 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 928 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3951 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3969 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3980 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3993 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 9854 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { in regime_using_lpae_format() 10083 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10089 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 10603 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 10665 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 10833 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | internals.h | 256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); in extended_addresses_enabled() 974 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3921 tcr->raw_tcr = value; in vmsa_ttbcr_raw_write() 3939 value = deposit64(tcr->raw_tcr, 0, 32, value); in vmsa_ttbcr_write() 3950 tcr->raw_tcr = 0; in vmsa_ttbcr_reset() 3963 tcr->raw_tcr = value; in vmsa_tcr_el12_write() 4464 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in tlbbits_for_regime() 10321 if (tcr->raw_tcr & TTBCR_PD1) { in get_level1_table_address() 10327 if (tcr->raw_tcr & TTBCR_PD0) { in get_level1_table_address() 10847 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa64_va_parameters() 10909 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; in aa32_va_parameters() 11096 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); in get_phys_addr_lpae() [all …]
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H A D | cpu.c | 209 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); in arm_cpu_reset()
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