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Searched refs:rd_rst_asreg_d2 (Results 1 – 2 of 2) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/
H A DFIFO_GENERATOR_V4_3.v865 reg rd_rst_asreg_d2 =0; register
1140 assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg;
1206 rd_rst_asreg_d2 <= rd_rst_asreg_d1;
H A DFIFO_GENERATOR_V6_1.v343 reg rd_rst_asreg_d2 = 0; register
941 assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg;
983 rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1;