1/* 2 * $RDCfile: $ $Revision: 1.1.2.15 $ $Date: 2007/07/25 15:58:33 $ 3 ******************************************************************************* 4 * 5 * FIFO Generator v3.3 - Verilog Behavioral Model 6 * 7 ******************************************************************************* 8 * 9 * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. 10 * This text/file contains proprietary, confidential 11 * information of Xilinx, Inc., is distributed under 12 * license from Xilinx, Inc., and may be used, copied 13 * and/or disclosed only pursuant to the terms of a valid 14 * license agreement with Xilinx, Inc. Xilinx hereby 15 * grants you a license to use this text/file solely for 16 * design, simulation, implementation and creation of 17 * design files limited to Xilinx devices or technologies. 18 * Use with non-Xilinx devices or technologies is expressly 19 * prohibited and immediately terminates your license unless 20 * covered by a separate agreement. 21 * 22 * Xilinx is providing theis design, code, or information 23 * "as-is" solely for use in developing programs and 24 * solutions for Xilinx devices, with no obligation on the 25 * part of Xilinx to provide support. By providing this design, 26 * code, or information as one possible implementation of 27 * this feature, application or standard. Xilinx is making no 28 * representation that this implementation is free from any 29 * claims of infringement. You are responsible for obtaining 30 * any rights you may require for your implementation. 31 * Xilinx expressly disclaims any warranty whatsoever with 32 * respect to the adequacy of the implementation, including 33 * but not limited to any warranties or representations that this 34 * implementation is free from claims of infringement, implied 35 * warranties of merchantability or fitness for a particular 36 * purpose. 37 * 38 * Xilinx products are not intended for use in life support 39 * appliances, devices, or systems. Use in such applications is 40 * expressly prohibited. 41 * 42 * This copyright and support notice must be retained as part 43 * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. 44 * All rights reserved. 45 * 46 ******************************************************************************* 47 * 48 * Filename: fifo_generator_v4_3_bhv.v 49 * 50 * Description: 51 * The verilog behavioral model for the FIFO generator core. 52 * 53 ******************************************************************************* 54 */ 55 56`timescale 1ps/1ps 57 58/******************************************************************************* 59 * Declaration of top-level module 60 ******************************************************************************/ 61module FIFO_GENERATOR_V4_3 62( 63 BACKUP, 64 BACKUP_MARKER, 65 CLK, 66 DIN, 67 PROG_EMPTY_THRESH, 68 PROG_EMPTY_THRESH_ASSERT, 69 PROG_EMPTY_THRESH_NEGATE, 70 PROG_FULL_THRESH, 71 PROG_FULL_THRESH_ASSERT, 72 PROG_FULL_THRESH_NEGATE, 73 RD_CLK, 74 RD_EN, 75 RD_RST, 76 RST, 77 SRST, 78 WR_CLK, 79 WR_EN, 80 WR_RST, 81 INT_CLK, 82 83 ALMOST_EMPTY, 84 ALMOST_FULL, 85 DATA_COUNT, 86 DOUT, 87 EMPTY, 88 FULL, 89 OVERFLOW, 90 PROG_EMPTY, 91 PROG_FULL, 92 RD_DATA_COUNT, 93 UNDERFLOW, 94 VALID, 95 WR_ACK, 96 WR_DATA_COUNT, 97 SBITERR, 98 DBITERR 99 ); 100 101 /**************************************************************************** 102 * Definition of Ports 103 * 104 * 105 ***************************************************************************** 106 * Definition of Parameters 107 * 108 * 109 *****************************************************************************/ 110 111 /**************************************************************************** 112 * Declare user parameters and their defaults 113 *****************************************************************************/ 114 parameter C_COMMON_CLOCK = 0; 115 parameter C_COUNT_TYPE = 0; 116 parameter C_DATA_COUNT_WIDTH = 2; 117 parameter C_DEFAULT_VALUE = ""; 118 parameter C_DIN_WIDTH = 8; 119 parameter C_DOUT_RST_VAL = ""; 120 parameter C_DOUT_WIDTH = 8; 121 parameter C_ENABLE_RLOCS = 0; 122 123 parameter C_FAMILY = "virtex2"; 124 //Not allowed in Verilog model 125 126 parameter C_HAS_ALMOST_EMPTY = 0; 127 parameter C_HAS_ALMOST_FULL = 0; 128 parameter C_HAS_BACKUP = 0; 129 parameter C_HAS_DATA_COUNT = 0; 130 parameter C_HAS_MEMINIT_FILE = 0; 131 parameter C_HAS_OVERFLOW = 0; 132 parameter C_HAS_RD_DATA_COUNT = 0; 133 parameter C_HAS_RD_RST = 0; 134 parameter C_HAS_RST = 0; 135 parameter C_HAS_SRST = 0; 136 parameter C_HAS_UNDERFLOW = 0; 137 parameter C_HAS_VALID = 0; 138 parameter C_HAS_WR_ACK = 0; 139 parameter C_HAS_WR_DATA_COUNT = 0; 140 parameter C_HAS_WR_RST = 0; 141 parameter C_IMPLEMENTATION_TYPE = 0; 142 parameter C_INIT_WR_PNTR_VAL = 0; 143 parameter C_MEMORY_TYPE = 1; 144 parameter C_MIF_FILE_NAME = ""; 145 parameter C_OPTIMIZATION_MODE = 0; 146 parameter C_OVERFLOW_LOW = 0; 147 parameter C_PRELOAD_LATENCY = 1; 148 parameter C_PRELOAD_REGS = 0; 149 parameter C_PRIM_FIFO_TYPE = 512; 150 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; 151 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; 152 parameter C_PROG_EMPTY_TYPE = 0; 153 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; 154 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; 155 parameter C_PROG_FULL_TYPE = 0; 156 parameter C_RD_DATA_COUNT_WIDTH = 2; 157 parameter C_RD_DEPTH = 256; 158 parameter C_RD_FREQ = 1; 159 parameter C_RD_PNTR_WIDTH = 8; 160 parameter C_UNDERFLOW_LOW = 0; 161 parameter C_USE_FIFO16_FLAGS = 0; 162 parameter C_VALID_LOW = 0; 163 parameter C_WR_ACK_LOW = 0; 164 parameter C_WR_DATA_COUNT_WIDTH = 2; 165 parameter C_WR_DEPTH = 256; 166 parameter C_WR_FREQ = 1; 167 parameter C_WR_PNTR_WIDTH = 8; 168 parameter C_WR_RESPONSE_LATENCY = 1; 169 parameter C_USE_ECC = 0; 170 parameter C_FULL_FLAGS_RST_VAL = 1; 171 parameter C_HAS_INT_CLK = 0; 172 parameter C_USE_EMBEDDED_REG = 0; 173 parameter C_USE_FWFT_DATA_COUNT = 0; 174 175 //There are 2 Verilog behavioral models 176 // 0 = Synchronous FIFO/ShiftRam FIFO 177 // 1 = Asynchronous FIFO 178 parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : 179 (C_IMPLEMENTATION_TYPE==1 ? 0 : 180 (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); 181 182 183 /****************************************************************************** 184 * Declare Input and Output Ports 185 *****************************************************************************/ 186 input CLK; 187 input BACKUP; 188 input BACKUP_MARKER; 189 input [C_DIN_WIDTH-1:0] DIN; 190 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; 191 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; 192 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; 193 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; 194 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; 195 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; 196 input RD_CLK; 197 input RD_EN; 198 input RD_RST; 199 input RST; 200 input SRST; 201 input WR_CLK; 202 input WR_EN; 203 input WR_RST; 204 input INT_CLK; 205 206 output ALMOST_EMPTY; 207 output ALMOST_FULL; 208 output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; 209 output [C_DOUT_WIDTH-1:0] DOUT; 210 output EMPTY; 211 output FULL; 212 output OVERFLOW; 213 output PROG_EMPTY; 214 output PROG_FULL; 215 output VALID; 216 output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; 217 output UNDERFLOW; 218 output WR_ACK; 219 output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; 220 output SBITERR; 221 output DBITERR; 222 223 224 wire ALMOST_EMPTY; 225 wire ALMOST_FULL; 226 wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; 227 wire [C_DOUT_WIDTH-1:0] DOUT; 228 wire EMPTY; 229 wire FULL; 230 wire OVERFLOW; 231 wire PROG_EMPTY; 232 wire PROG_FULL; 233 wire VALID; 234 wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; 235 wire UNDERFLOW; 236 wire WR_ACK; 237 wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; 238 239 240 wire RD_CLK_P0_IN; 241 wire RST_P0_IN; 242 wire RD_EN_FIFO_IN; 243 wire RD_EN_P0_IN; 244 245 wire ALMOST_EMPTY_FIFO_OUT; 246 wire ALMOST_FULL_FIFO_OUT; 247 wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; 248 wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; 249 wire EMPTY_FIFO_OUT; 250 wire FULL_FIFO_OUT; 251 wire OVERFLOW_FIFO_OUT; 252 wire PROG_EMPTY_FIFO_OUT; 253 wire PROG_FULL_FIFO_OUT; 254 wire VALID_FIFO_OUT; 255 wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; 256 wire UNDERFLOW_FIFO_OUT; 257 wire WR_ACK_FIFO_OUT; 258 wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; 259 260 261 //*************************************************************************** 262 // Internal Signals 263 // The core uses either the internal_ wires or the preload0_ wires depending 264 // on whether the core uses Preload0 or not. 265 // When using preload0, the internal signals connect the internal core to 266 // the preload logic, and the external core's interfaces are tied to the 267 // preload0 signals from the preload logic. 268 //*************************************************************************** 269 wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; 270 wire VALID_P0_OUT; 271 wire EMPTY_P0_OUT; 272 wire ALMOSTEMPTY_P0_OUT; 273 reg EMPTY_P0_OUT_Q; 274 reg ALMOSTEMPTY_P0_OUT_Q; 275 wire UNDERFLOW_P0_OUT; 276 wire RDEN_P0_OUT; 277 wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; 278 wire EMPTY_P0_IN; 279 280 assign SBITERR = 1'b0; 281 assign DBITERR = 1'b0; 282 283// choose the base FIFO implementation for simulation 284generate 285case (C_VERILOG_IMPL) 2860 : begin : block1 287 fifo_generator_v4_3_bhv_ver_ss 288 #( 289 C_COMMON_CLOCK, 290 C_COUNT_TYPE, 291 C_DATA_COUNT_WIDTH, 292 C_DEFAULT_VALUE, 293 C_DIN_WIDTH, 294 C_DOUT_RST_VAL, 295 C_DOUT_WIDTH, 296 C_ENABLE_RLOCS, 297 C_FAMILY,//Not allowed in Verilog model 298 C_HAS_ALMOST_EMPTY, 299 C_HAS_ALMOST_FULL, 300 C_HAS_BACKUP, 301 C_HAS_DATA_COUNT, 302 C_HAS_MEMINIT_FILE, 303 C_HAS_OVERFLOW, 304 C_HAS_RD_DATA_COUNT, 305 C_HAS_RD_RST, 306 C_HAS_RST, 307 C_HAS_SRST, 308 C_HAS_UNDERFLOW, 309 C_HAS_VALID, 310 C_HAS_WR_ACK, 311 C_HAS_WR_DATA_COUNT, 312 C_HAS_WR_RST, 313 C_IMPLEMENTATION_TYPE, 314 C_INIT_WR_PNTR_VAL, 315 C_MEMORY_TYPE, 316 C_MIF_FILE_NAME, 317 C_OPTIMIZATION_MODE, 318 C_OVERFLOW_LOW, 319 C_PRELOAD_LATENCY, 320 C_PRELOAD_REGS, 321 C_PROG_EMPTY_THRESH_ASSERT_VAL, 322 C_PROG_EMPTY_THRESH_NEGATE_VAL, 323 C_PROG_EMPTY_TYPE, 324 C_PROG_FULL_THRESH_ASSERT_VAL, 325 C_PROG_FULL_THRESH_NEGATE_VAL, 326 C_PROG_FULL_TYPE, 327 C_RD_DATA_COUNT_WIDTH, 328 C_RD_DEPTH, 329 C_RD_PNTR_WIDTH, 330 C_UNDERFLOW_LOW, 331 C_VALID_LOW, 332 C_WR_ACK_LOW, 333 C_WR_DATA_COUNT_WIDTH, 334 C_WR_DEPTH, 335 C_WR_PNTR_WIDTH, 336 C_WR_RESPONSE_LATENCY, 337 C_FULL_FLAGS_RST_VAL, 338 C_USE_EMBEDDED_REG 339 ) 340 gen_ss 341 ( 342 .CLK (CLK), 343 .RST (RST), 344 .SRST (SRST), 345 .DIN (DIN), 346 .WR_EN (WR_EN), 347 .RD_EN (RD_EN_FIFO_IN), 348 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 349 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 350 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 351 .PROG_FULL_THRESH (PROG_FULL_THRESH), 352 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 353 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 354 .DOUT (DOUT_FIFO_OUT), 355 .FULL (FULL_FIFO_OUT), 356 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 357 .WR_ACK (WR_ACK_FIFO_OUT), 358 .OVERFLOW (OVERFLOW_FIFO_OUT), 359 .EMPTY (EMPTY_FIFO_OUT), 360 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 361 .VALID (VALID_FIFO_OUT), 362 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 363 .DATA_COUNT (DATA_COUNT_FIFO_OUT), 364 .PROG_FULL (PROG_FULL_FIFO_OUT), 365 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) 366 ); 367end 3681 : begin : block1 369 fifo_generator_v4_3_bhv_ver_as 370 #( 371 C_COMMON_CLOCK, 372 C_COUNT_TYPE, 373 C_DATA_COUNT_WIDTH, 374 C_DEFAULT_VALUE, 375 C_DIN_WIDTH, 376 C_DOUT_RST_VAL, 377 C_DOUT_WIDTH, 378 C_ENABLE_RLOCS, 379 C_FAMILY,//Not allowed in Verilog model 380 C_HAS_ALMOST_EMPTY, 381 C_HAS_ALMOST_FULL, 382 C_HAS_BACKUP, 383 C_HAS_DATA_COUNT, 384 C_HAS_MEMINIT_FILE, 385 C_HAS_OVERFLOW, 386 C_HAS_RD_DATA_COUNT, 387 C_HAS_RD_RST, 388 C_HAS_RST, 389 C_HAS_UNDERFLOW, 390 C_HAS_VALID, 391 C_HAS_WR_ACK, 392 C_HAS_WR_DATA_COUNT, 393 C_HAS_WR_RST, 394 C_IMPLEMENTATION_TYPE, 395 C_INIT_WR_PNTR_VAL, 396 C_MEMORY_TYPE, 397 C_MIF_FILE_NAME, 398 C_OPTIMIZATION_MODE, 399 C_OVERFLOW_LOW, 400 C_PRELOAD_LATENCY, 401 C_PRELOAD_REGS, 402 C_PROG_EMPTY_THRESH_ASSERT_VAL, 403 C_PROG_EMPTY_THRESH_NEGATE_VAL, 404 C_PROG_EMPTY_TYPE, 405 C_PROG_FULL_THRESH_ASSERT_VAL, 406 C_PROG_FULL_THRESH_NEGATE_VAL, 407 C_PROG_FULL_TYPE, 408 C_RD_DATA_COUNT_WIDTH, 409 C_RD_DEPTH, 410 C_RD_PNTR_WIDTH, 411 C_UNDERFLOW_LOW, 412 C_VALID_LOW, 413 C_WR_ACK_LOW, 414 C_WR_DATA_COUNT_WIDTH, 415 C_WR_DEPTH, 416 C_WR_PNTR_WIDTH, 417 C_WR_RESPONSE_LATENCY, 418 C_FULL_FLAGS_RST_VAL, 419 C_USE_FWFT_DATA_COUNT, 420 C_USE_EMBEDDED_REG 421 ) 422 gen_as 423 ( 424 .WR_CLK (WR_CLK), 425 .RD_CLK (RD_CLK), 426 .RST (RST), 427 .DIN (DIN), 428 .WR_EN (WR_EN), 429 .RD_EN (RD_EN_FIFO_IN), 430 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 431 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 432 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 433 .PROG_FULL_THRESH (PROG_FULL_THRESH), 434 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 435 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 436 .DOUT (DOUT_FIFO_OUT), 437 .FULL (FULL_FIFO_OUT), 438 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 439 .WR_ACK (WR_ACK_FIFO_OUT), 440 .OVERFLOW (OVERFLOW_FIFO_OUT), 441 .EMPTY (EMPTY_FIFO_OUT), 442 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 443 .VALID (VALID_FIFO_OUT), 444 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 445 .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), 446 .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), 447 .PROG_FULL (PROG_FULL_FIFO_OUT), 448 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) 449 ); 450end 451 452default : begin : block1 453 fifo_generator_v4_3_bhv_ver_as 454 #( 455 C_COMMON_CLOCK, 456 C_COUNT_TYPE, 457 C_DATA_COUNT_WIDTH, 458 C_DEFAULT_VALUE, 459 C_DIN_WIDTH, 460 C_DOUT_RST_VAL, 461 C_DOUT_WIDTH, 462 C_ENABLE_RLOCS, 463 C_FAMILY,//Not allowed in Verilog model 464 C_HAS_ALMOST_EMPTY, 465 C_HAS_ALMOST_FULL, 466 C_HAS_BACKUP, 467 C_HAS_DATA_COUNT, 468 C_HAS_MEMINIT_FILE, 469 C_HAS_OVERFLOW, 470 C_HAS_RD_DATA_COUNT, 471 C_HAS_RD_RST, 472 C_HAS_RST, 473 C_HAS_UNDERFLOW, 474 C_HAS_VALID, 475 C_HAS_WR_ACK, 476 C_HAS_WR_DATA_COUNT, 477 C_HAS_WR_RST, 478 C_IMPLEMENTATION_TYPE, 479 C_INIT_WR_PNTR_VAL, 480 C_MEMORY_TYPE, 481 C_MIF_FILE_NAME, 482 C_OPTIMIZATION_MODE, 483 C_OVERFLOW_LOW, 484 C_PRELOAD_LATENCY, 485 C_PRELOAD_REGS, 486 C_PROG_EMPTY_THRESH_ASSERT_VAL, 487 C_PROG_EMPTY_THRESH_NEGATE_VAL, 488 C_PROG_EMPTY_TYPE, 489 C_PROG_FULL_THRESH_ASSERT_VAL, 490 C_PROG_FULL_THRESH_NEGATE_VAL, 491 C_PROG_FULL_TYPE, 492 C_RD_DATA_COUNT_WIDTH, 493 C_RD_DEPTH, 494 C_RD_PNTR_WIDTH, 495 C_UNDERFLOW_LOW, 496 C_VALID_LOW, 497 C_WR_ACK_LOW, 498 C_WR_DATA_COUNT_WIDTH, 499 C_WR_DEPTH, 500 C_WR_PNTR_WIDTH, 501 C_WR_RESPONSE_LATENCY, 502 C_FULL_FLAGS_RST_VAL, 503 C_USE_FWFT_DATA_COUNT, 504 C_USE_EMBEDDED_REG 505 ) 506 gen_as 507 ( 508 .WR_CLK (WR_CLK), 509 .RD_CLK (RD_CLK), 510 .RST (RST), 511 .DIN (DIN), 512 .WR_EN (WR_EN), 513 .RD_EN (RD_EN_FIFO_IN), 514 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 515 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 516 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 517 .PROG_FULL_THRESH (PROG_FULL_THRESH), 518 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 519 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 520 .DOUT (DOUT_FIFO_OUT), 521 .FULL (FULL_FIFO_OUT), 522 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 523 .WR_ACK (WR_ACK_FIFO_OUT), 524 .OVERFLOW (OVERFLOW_FIFO_OUT), 525 .EMPTY (EMPTY_FIFO_OUT), 526 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 527 .VALID (VALID_FIFO_OUT), 528 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 529 .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), 530 .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), 531 .PROG_FULL (PROG_FULL_FIFO_OUT), 532 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) 533 ); 534end 535 536endcase 537endgenerate 538 539 540//************************************************************************** 541// Connect Internal Signals 542// (Signals labeled internal_*) 543// In the normal case, these signals tie directly to the FIFO's inputs and 544// outputs. 545// In the case of Preload Latency 0 or 1, there are intermediate 546// signals between the internal FIFO and the preload logic. 547//************************************************************************** 548 549generate 550if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 551 begin : block2 552 553fifo_generator_v4_3_bhv_ver_preload0 554 #( 555 C_DOUT_RST_VAL, 556 C_DOUT_WIDTH, 557 C_HAS_RST, 558 C_VALID_LOW, 559 C_UNDERFLOW_LOW 560 ) 561 fgpl0 562( 563 .RD_CLK (RD_CLK_P0_IN), 564 .RD_RST (RST_P0_IN), 565 .RD_EN (RD_EN_P0_IN), 566 .FIFOEMPTY (EMPTY_P0_IN), 567 .FIFODATA (DATA_P0_IN), 568 .USERDATA (DATA_P0_OUT), 569 .USERVALID (VALID_P0_OUT), 570 .USEREMPTY (EMPTY_P0_OUT), 571 .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), 572 .USERUNDERFLOW (UNDERFLOW_P0_OUT), 573 .RAMVALID (RAMVALID_P0_OUT), 574 .FIFORDEN (RDEN_P0_OUT) 575 ); 576 577 assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); 578 assign RST_P0_IN = RST; 579 assign RD_EN_P0_IN = RD_EN; 580 581 assign RD_EN_FIFO_IN = RDEN_P0_OUT; 582 583 assign DOUT = DATA_P0_OUT; 584 assign DATA_P0_IN = DOUT_FIFO_OUT; 585 assign VALID = VALID_P0_OUT ; 586 assign EMPTY = EMPTY_P0_OUT; 587 assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; 588 assign EMPTY_P0_IN = EMPTY_FIFO_OUT; 589 assign UNDERFLOW = UNDERFLOW_P0_OUT ; 590 591 always @ (posedge RD_CLK or posedge RST) 592 begin 593 if (RST) 594 begin 595 EMPTY_P0_OUT_Q <= 1; 596 ALMOSTEMPTY_P0_OUT_Q <= 1; 597 end 598 else 599 begin 600 EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; 601 ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; 602 end 603 end 604 605 end 606else 607 begin : block2 608 609 assign RD_CLK_P0_IN = 0; 610 assign RST_P0_IN = 0; 611 assign RD_EN_P0_IN = 0; 612 613 assign RD_EN_FIFO_IN = RD_EN; 614 615 assign DOUT = DOUT_FIFO_OUT; 616 assign DATA_P0_IN = 0; 617 assign VALID = VALID_FIFO_OUT; 618 assign EMPTY = EMPTY_FIFO_OUT; 619 assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; 620 assign EMPTY_P0_IN = 0; 621 assign UNDERFLOW = UNDERFLOW_FIFO_OUT; 622 623 end 624endgenerate 625 626 627//Connect Data Count Signals 628generate 629if (C_USE_FWFT_DATA_COUNT==1) begin : block3 630 assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); 631end 632else begin : block3 633 assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; 634end 635endgenerate 636 637generate 638if (C_USE_FWFT_DATA_COUNT==1) begin : block4 639 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; 640end 641else begin : block4 642 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; 643end 644endgenerate 645 646 647 assign FULL = FULL_FIFO_OUT; 648 assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; 649 assign WR_ACK = WR_ACK_FIFO_OUT; 650 assign OVERFLOW = OVERFLOW_FIFO_OUT; 651 assign PROG_FULL = PROG_FULL_FIFO_OUT; 652 assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; 653 assign DATA_COUNT = DATA_COUNT_FIFO_OUT; 654 655 656 // if an asynchronous FIFO has been selected, display a message that the FIFO 657 // will not be cycle-accurate in simulation 658 initial begin 659 //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1 660 if (C_IMPLEMENTATION_TYPE == 2) begin //fixed in v3.2 (IP2_Im) 661 $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); 662 end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin 663 $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); 664 $finish; 665 end 666 667 end 668 669endmodule //fifo_generator_v4_3_bhv_ver 670 671 672 673 674 675 676/******************************************************************************* 677 * Declaration of asynchronous FIFO Module 678 ******************************************************************************/ 679module fifo_generator_v4_3_bhv_ver_as 680 ( 681 WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, 682 PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, 683 PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, 684 DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, 685 UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY 686 ); 687 688 /***************************************************************************** 689 * Declare user parameters and their defaults 690 *****************************************************************************/ 691 parameter C_COMMON_CLOCK = 0; 692 parameter C_COUNT_TYPE = 0; 693 parameter C_DATA_COUNT_WIDTH = 2; 694 parameter C_DEFAULT_VALUE = ""; 695 parameter C_DIN_WIDTH = 8; 696 parameter C_DOUT_RST_VAL = ""; 697 parameter C_DOUT_WIDTH = 8; 698 parameter C_ENABLE_RLOCS = 0; 699 parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model 700 parameter C_HAS_ALMOST_EMPTY = 0; 701 parameter C_HAS_ALMOST_FULL = 0; 702 parameter C_HAS_BACKUP = 0; 703 parameter C_HAS_DATA_COUNT = 0; 704 parameter C_HAS_MEMINIT_FILE = 0; 705 parameter C_HAS_OVERFLOW = 0; 706 parameter C_HAS_RD_DATA_COUNT = 0; 707 parameter C_HAS_RD_RST = 0; 708 parameter C_HAS_RST = 0; 709 parameter C_HAS_UNDERFLOW = 0; 710 parameter C_HAS_VALID = 0; 711 parameter C_HAS_WR_ACK = 0; 712 parameter C_HAS_WR_DATA_COUNT = 0; 713 parameter C_HAS_WR_RST = 0; 714 parameter C_IMPLEMENTATION_TYPE = 0; 715 parameter C_INIT_WR_PNTR_VAL = 0; 716 parameter C_MEMORY_TYPE = 1; 717 parameter C_MIF_FILE_NAME = ""; 718 parameter C_OPTIMIZATION_MODE = 0; 719 parameter C_OVERFLOW_LOW = 0; 720 parameter C_PRELOAD_LATENCY = 1; 721 parameter C_PRELOAD_REGS = 0; 722 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; 723 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; 724 parameter C_PROG_EMPTY_TYPE = 0; 725 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; 726 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; 727 parameter C_PROG_FULL_TYPE = 0; 728 parameter C_RD_DATA_COUNT_WIDTH = 2; 729 parameter C_RD_DEPTH = 256; 730 parameter C_RD_PNTR_WIDTH = 8; 731 parameter C_UNDERFLOW_LOW = 0; 732 parameter C_VALID_LOW = 0; 733 parameter C_WR_ACK_LOW = 0; 734 parameter C_WR_DATA_COUNT_WIDTH = 2; 735 parameter C_WR_DEPTH = 256; 736 parameter C_WR_PNTR_WIDTH = 8; 737 parameter C_WR_RESPONSE_LATENCY = 1; 738 parameter C_FULL_FLAGS_RST_VAL = 1; 739 parameter C_USE_FWFT_DATA_COUNT = 0; 740 parameter C_USE_EMBEDDED_REG = 0; 741 742 /***************************************************************************** 743 * Declare Input and Output Ports 744 *****************************************************************************/ 745 input [C_DIN_WIDTH-1:0] DIN; 746 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; 747 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; 748 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; 749 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; 750 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; 751 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; 752 input RD_CLK; 753 input RD_EN; 754 input RST; 755 input WR_CLK; 756 input WR_EN; 757 output ALMOST_EMPTY; 758 output ALMOST_FULL; 759 output [C_DOUT_WIDTH-1:0] DOUT; 760 output EMPTY; 761 output FULL; 762 output OVERFLOW; 763 output PROG_EMPTY; 764 output PROG_FULL; 765 output VALID; 766 output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; 767 output UNDERFLOW; 768 output WR_ACK; 769 output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; 770 771 /******************************************************************************* 772 * Input and output register declarations 773 ******************************************************************************/ 774 /******************************************************************************* 775 * Parameters used as constants 776 ******************************************************************************/ 777 //When RST is present, set FULL reset value to '1'. 778 //If core has no RST, make sure FULL powers-on as '0'. 779 parameter C_DEPTH_RATIO_WR = 780 (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; 781 parameter C_DEPTH_RATIO_RD = 782 (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; 783 parameter C_FIFO_WR_DEPTH = 784 (C_COMMON_CLOCK) ? 785 C_WR_DEPTH : C_WR_DEPTH - 1; 786 parameter C_FIFO_RD_DEPTH = 787 (C_COMMON_CLOCK) ? 788 C_RD_DEPTH : C_RD_DEPTH - 1; 789 790 791 // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD 792 // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 793 // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) 794 // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 795 // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 796 parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); 797 // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD 798 // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC 799 // -----------------|------------------|-----------------|--------------- 800 // 1 | 8 | C_RD_PNTR_WIDTH | 2 801 // 1 | 4 | C_RD_PNTR_WIDTH | 2 802 // 1 | 2 | C_RD_PNTR_WIDTH | 2 803 // 1 | 1 | C_WR_PNTR_WIDTH | 2 804 // 2 | 1 | C_WR_PNTR_WIDTH | 4 805 // 4 | 1 | C_WR_PNTR_WIDTH | 8 806 // 8 | 1 | C_WR_PNTR_WIDTH | 16 807 parameter EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR)? 808 2:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); 809 810 811 //Memory which will be used to simulate a FIFO 812 reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; 813 reg [31:0] num_wr_bits; 814 reg [31:0] num_rd_bits; 815 reg [31:0] next_num_wr_bits; 816 reg [31:0] next_num_rd_bits; 817 reg [31:0] wr_ptr; 818 reg [31:0] rd_ptr; 819 reg [31:0] wr_ptr_rdclk; 820 reg [31:0] wr_ptr_rdclk_next; 821 reg [31:0] rd_ptr_wrclk; 822 reg [31:0] rd_ptr_wrclk_next; 823 wire [31:0] num_read_words = num_rd_bits/C_DOUT_WIDTH; 824 wire [31:0] num_read_words_dc_i; 825 wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; 826 wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); 827 wire [31:0] num_read_words_pe = 828 num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); 829 wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; 830 wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized 831 = num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; 832 wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft 833 = num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; 834 wire [31:0] num_write_words = num_wr_bits/C_DIN_WIDTH; 835 wire [31:0] num_write_words_dc_i; 836 wire [31:0] num_write_words_dc = 1+(num_wr_bits-1)/C_DIN_WIDTH;//roof of num_wr_bits/C_DIN_WIDTH 837 wire [31:0] num_write_words_fwft_dc = 838 (num_wr_bits/C_DIN_WIDTH*C_DEPTH_RATIO_RD+2*C_DEPTH_RATIO_WR)/C_DEPTH_RATIO_RD; 839 wire [31:0] num_write_words_pf = 840 num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); 841 wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; 842 wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized 843 = num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; 844 wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft 845 = num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; 846 wire [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; 847 wire [31:0] log2_reads_per_write = log2_val(reads_per_write); 848 wire [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; 849 wire [31:0] log2_writes_per_read = log2_val(writes_per_read); 850 851 /******************************************************************************* 852 * Internal Registers and wires 853 ******************************************************************************/ 854 wire wr_ack_i; 855 wire overflow_i; 856 wire underflow_i; 857 wire valid_i; 858 wire valid_out; 859 reg valid_d1; 860 /******************************************************************************* 861 * Internal registers and wires for internal reset logics 862 ******************************************************************************/ 863 reg rd_rst_asreg =0; 864 reg rd_rst_asreg_d1 =0; 865 reg rd_rst_asreg_d2 =0; 866 reg rd_rst_reg =0; 867 reg rd_rst_d1 =0; 868 reg wr_rst_asreg =0; 869 reg wr_rst_asreg_d1 =0; 870 reg wr_rst_asreg_d2 =0; 871 reg wr_rst_reg =0; 872 reg wr_rst_d1 =0; 873 wire rd_rst_comb; 874 wire rd_rst_i; 875 wire wr_rst_comb; 876 wire wr_rst_i; 877 878 879 880 //Special ideal FIFO signals 881 reg [C_DOUT_WIDTH-1:0] ideal_dout; 882 wire [C_DOUT_WIDTH-1:0] ideal_dout_out; 883 reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; 884 reg ideal_wr_ack; 885 reg ideal_valid; 886 reg ideal_overflow; 887 reg ideal_underflow; 888 reg ideal_full; 889 reg ideal_empty; 890 reg ideal_almost_full; 891 reg ideal_almost_empty; 892 reg ideal_prog_full; 893 reg ideal_prog_empty; 894 895 //MSBs of the counts 896 reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; 897 reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; 898 899 //user specified value for reseting the size of the fifo 900 reg [C_DOUT_WIDTH-1:0] dout_reset_val; 901 902 //temporary registers for WR_RESPONSE_LATENCY feature 903 904 integer tmp_wr_listsize; 905 integer tmp_rd_listsize; 906 907 //Signal for registered version of prog full and empty 908 reg prog_full_d; 909 reg prog_empty_d; 910 911 //Threshold values for Programmable Flags 912 integer prog_empty_actual_thresh_assert; 913 integer prog_empty_actual_thresh_negate; 914 integer prog_full_actual_thresh_assert; 915 integer prog_full_actual_thresh_negate; 916 917 918 /**************************************************************************** 919 * Function Declarations 920 ***************************************************************************/ 921 922 task write_fifo; 923 begin 924 memory[wr_ptr] <= DIN; 925 if (wr_ptr == 0) begin 926 wr_ptr <= C_WR_DEPTH - 1; 927 end else begin 928 wr_ptr <= wr_ptr - 1; 929 end 930 end 931 endtask // write_fifo 932 933 task read_fifo; 934 integer i; 935 reg [C_DOUT_WIDTH-1:0] tmp_dout; 936 reg [C_DIN_WIDTH-1:0] memory_read; 937 reg [31:0] tmp_rd_ptr; 938 reg [31:0] rd_ptr_high; 939 reg [31:0] rd_ptr_low; 940 begin 941 // output is wider than input 942 if (reads_per_write == 0) begin 943 tmp_dout = 0; 944 tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); 945 for (i = writes_per_read - 1; i >= 0; i = i - 1) begin 946 tmp_dout = tmp_dout << C_DIN_WIDTH; 947 tmp_dout = tmp_dout | memory[tmp_rd_ptr]; 948 if (tmp_rd_ptr == 0) begin 949 tmp_rd_ptr = C_WR_DEPTH - 1; 950 end else begin 951 tmp_rd_ptr = tmp_rd_ptr - 1; 952 end 953 end 954 955 // output is symmetric 956 end else if (reads_per_write == 1) begin 957 tmp_dout = memory[rd_ptr]; 958 959 // input is wider than output 960 end else begin 961 rd_ptr_high = rd_ptr >> log2_reads_per_write; 962 rd_ptr_low = rd_ptr & (reads_per_write - 1); 963 memory_read = memory[rd_ptr_high]; 964 tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); 965 end 966 ideal_dout <= tmp_dout; 967 if (rd_ptr == 0) begin 968 rd_ptr <= C_RD_DEPTH - 1; 969 end else begin 970 rd_ptr <= rd_ptr - 1; 971 end 972 end 973 endtask 974 975 /**************************************************************************** 976 * log2_val 977 * Returns the 'log2' value for the input value for the supported ratios 978 ***************************************************************************/ 979 function [31:0] log2_val; 980 input [31:0] binary_val; 981 982 begin 983 if (binary_val == 8) begin 984 log2_val = 3; 985 end else if (binary_val == 4) begin 986 log2_val = 2; 987 end else begin 988 log2_val = 1; 989 end 990 end 991 endfunction 992 993 /************************************************************************* 994 * hexstr_conv 995 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 996 ***********************************************************************/ 997 function [C_DOUT_WIDTH-1:0] hexstr_conv; 998 input [(C_DOUT_WIDTH*8)-1:0] def_data; 999 1000 integer index,i,j; 1001 reg [3:0] bin; 1002 1003 begin 1004 index = 0; 1005 hexstr_conv = 'b0; 1006 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 1007 begin 1008 case (def_data[7:0]) 1009 8'b00000000 : 1010 begin 1011 bin = 4'b0000; 1012 i = -1; 1013 end 1014 8'b00110000 : bin = 4'b0000; 1015 8'b00110001 : bin = 4'b0001; 1016 8'b00110010 : bin = 4'b0010; 1017 8'b00110011 : bin = 4'b0011; 1018 8'b00110100 : bin = 4'b0100; 1019 8'b00110101 : bin = 4'b0101; 1020 8'b00110110 : bin = 4'b0110; 1021 8'b00110111 : bin = 4'b0111; 1022 8'b00111000 : bin = 4'b1000; 1023 8'b00111001 : bin = 4'b1001; 1024 8'b01000001 : bin = 4'b1010; 1025 8'b01000010 : bin = 4'b1011; 1026 8'b01000011 : bin = 4'b1100; 1027 8'b01000100 : bin = 4'b1101; 1028 8'b01000101 : bin = 4'b1110; 1029 8'b01000110 : bin = 4'b1111; 1030 8'b01100001 : bin = 4'b1010; 1031 8'b01100010 : bin = 4'b1011; 1032 8'b01100011 : bin = 4'b1100; 1033 8'b01100100 : bin = 4'b1101; 1034 8'b01100101 : bin = 4'b1110; 1035 8'b01100110 : bin = 4'b1111; 1036 default : 1037 begin 1038 bin = 4'bx; 1039 end 1040 endcase 1041 for( j=0; j<4; j=j+1) 1042 begin 1043 if ((index*4)+j < C_DOUT_WIDTH) 1044 begin 1045 hexstr_conv[(index*4)+j] = bin[j]; 1046 end 1047 end 1048 index = index + 1; 1049 def_data = def_data >> 8; 1050 end 1051 end 1052 endfunction 1053 1054 /************************************************************************* 1055 * Initialize Signals for clean power-on simulation 1056 *************************************************************************/ 1057 initial 1058 begin 1059 num_wr_bits = 0; 1060 num_rd_bits = 0; 1061 next_num_wr_bits = 0; 1062 next_num_rd_bits = 0; 1063 rd_ptr = C_RD_DEPTH - 1; 1064 wr_ptr = C_WR_DEPTH - 1; 1065 rd_ptr_wrclk = rd_ptr; 1066 wr_ptr_rdclk = wr_ptr; 1067 dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); 1068 ideal_dout = dout_reset_val; 1069 ideal_wr_ack = 1'b0; 1070 ideal_valid = 1'b0; 1071 ideal_overflow = 1'b0; 1072 ideal_underflow = 1'b0; 1073 //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) 1074 //ideal_full = C_FULL_RESET_VAL; //was in v3.1 1075 ideal_full = 1'b0; //v3.2 1076 ideal_empty = 1'b1; 1077 //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) 1078 //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 1079 ideal_almost_full = 1'b0; //v3.2 1080 ideal_almost_empty = 1'b1; 1081 ideal_wr_count = 0; 1082 ideal_rd_count = 0; 1083 //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) 1084 //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 1085 ideal_prog_full = 1'b0; //v3.2 1086 ideal_prog_empty = 1'b1; 1087 //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) 1088 //Therefore, prog_full_d has to start-up at '0' too 1089 //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 1090 prog_full_d = 1'b0; //v3.2 1091 prog_empty_d = 1'b1; 1092 end 1093 1094 1095 1096 /************************************************************************* 1097 * Assign Internal ideal signals to output ports 1098 *************************************************************************/ 1099 assign ideal_dout_out= (C_PRELOAD_LATENCY==2 && 1100 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 1101 ideal_dout_d1: ideal_dout; 1102 assign DOUT = ideal_dout_out; 1103 assign FULL = ideal_full; 1104 assign EMPTY = ideal_empty; 1105 assign ALMOST_FULL = ideal_almost_full; 1106 assign ALMOST_EMPTY = ideal_almost_empty; 1107 assign num_write_words_sized_i=C_USE_FWFT_DATA_COUNT? 1108 num_write_words_sized_fwft:num_write_words_sized; 1109 assign num_read_words_sized_i=C_USE_FWFT_DATA_COUNT? 1110 num_read_words_sized_fwft:num_read_words_sized; 1111 assign num_write_words_dc_i = C_USE_FWFT_DATA_COUNT? 1112 num_write_words_fwft_dc: num_write_words_dc; 1113 assign num_read_words_dc_i = C_USE_FWFT_DATA_COUNT? 1114 num_read_words_fwft_dc: num_read_words_dc; 1115 assign WR_DATA_COUNT = ideal_wr_count; 1116 assign RD_DATA_COUNT = ideal_rd_count; 1117 assign PROG_FULL = ideal_prog_full; 1118 assign PROG_EMPTY = ideal_prog_empty; 1119 1120 //Handshaking signals can be active low, depending on _LOW parameters 1121 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; 1122 assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; 1123 assign valid_out = (C_PRELOAD_LATENCY==2 && 1124 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 1125 valid_d1: valid_i; 1126 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; 1127 assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; 1128 1129 assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; 1130 assign wr_ack_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : 1131 (WR_EN & !FULL); 1132 assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; 1133 assign overflow_i = (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : 1134 (WR_EN & FULL); 1135 1136 /******************************************************************************* 1137 * Internal reset logics 1138 ******************************************************************************/ 1139 assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; 1140 assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; 1141 assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; 1142 assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; 1143 1144 1145 always @(posedge RD_CLK or posedge rd_rst_i) begin 1146 if (rd_rst_i == 1'b1) begin 1147 valid_d1 <= 1'b0; 1148 end else begin 1149 valid_d1 <= valid_i; 1150 end 1151 end 1152 always @(posedge RD_CLK or posedge rd_rst_i) begin 1153 if (rd_rst_i == 1'b1) begin 1154 ideal_dout_d1 <= dout_reset_val; 1155 end else begin 1156 ideal_dout_d1 <= ideal_dout; 1157 end 1158 end 1159 1160 always @(posedge WR_CLK or posedge RST) begin 1161 if (RST == 1'b1) begin 1162 wr_rst_asreg <= 1'b1; 1163 end else begin 1164 if (wr_rst_asreg_d1 == 1'b1) begin 1165 wr_rst_asreg <= 1'b0; 1166 end else begin 1167 wr_rst_asreg <= wr_rst_asreg; 1168 end 1169 end 1170 end 1171 1172 always @(posedge WR_CLK) begin 1173 wr_rst_asreg_d1 <= wr_rst_asreg; 1174 wr_rst_asreg_d2 <= wr_rst_asreg_d1; 1175 end 1176 1177 always @(posedge WR_CLK or posedge wr_rst_comb) begin 1178 if (wr_rst_comb == 1'b1) begin 1179 wr_rst_reg <= 1'b1; 1180 end else begin 1181 wr_rst_reg <= 1'b0; 1182 end 1183 end 1184 1185 always @(posedge WR_CLK or posedge wr_rst_i) begin 1186 if (wr_rst_i == 1'b1) begin 1187 wr_rst_d1 <= 1'b1; 1188 end else begin 1189 wr_rst_d1 <= wr_rst_i; 1190 end 1191 end 1192 always @(posedge RD_CLK or posedge RST) begin 1193 if (RST == 1'b1) begin 1194 rd_rst_asreg <= 1'b1; 1195 end else begin 1196 if (rd_rst_asreg_d1 == 1'b1) begin 1197 rd_rst_asreg <= 1'b0; 1198 end else begin 1199 rd_rst_asreg <= rd_rst_asreg; 1200 end 1201 end 1202 end 1203 1204 always @(posedge RD_CLK) begin 1205 rd_rst_asreg_d1 <= rd_rst_asreg; 1206 rd_rst_asreg_d2 <= rd_rst_asreg_d1; 1207 end 1208 1209 always @(posedge RD_CLK or posedge rd_rst_comb) begin 1210 if (rd_rst_comb == 1'b1) begin 1211 rd_rst_reg <= 1'b1; 1212 end else begin 1213 rd_rst_reg <= 1'b0; 1214 end 1215 end 1216 1217 //Generate overflow and underflow flags seperately 1218 //because they don't support async rst 1219 always @(posedge WR_CLK) begin 1220 ideal_overflow <= WR_EN & ideal_full; 1221 end 1222 always @(posedge RD_CLK) begin 1223 ideal_underflow <= ideal_empty & RD_EN; 1224 end 1225 1226 /******************************************************************************* 1227 * Write and Read Logics 1228 ******************************************************************************/ 1229 always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w 1230 1231 /****** Reset fifo (case 1)***************************************/ 1232 if (wr_rst_i == 1'b1) begin 1233 num_wr_bits <= 0; 1234 next_num_wr_bits <= 0; 1235 wr_ptr <= C_WR_DEPTH - 1; 1236 rd_ptr_wrclk <= C_RD_DEPTH - 1; 1237 ideal_wr_ack <= 0; 1238 ideal_full <= C_FULL_FLAGS_RST_VAL; 1239 ideal_almost_full <= C_FULL_FLAGS_RST_VAL; 1240 ideal_wr_count <= 0; 1241 1242 ideal_prog_full <= C_FULL_FLAGS_RST_VAL; 1243 prog_full_d <= C_FULL_FLAGS_RST_VAL; 1244 1245 end else begin //wr_rst_i==0 1246 1247 //Determine the current number of words in the FIFO 1248 tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : 1249 num_wr_bits/C_DIN_WIDTH; 1250 rd_ptr_wrclk_next = rd_ptr; 1251 if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin 1252 next_num_wr_bits = num_wr_bits - 1253 C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH 1254 - rd_ptr_wrclk_next); 1255 end else begin 1256 next_num_wr_bits = num_wr_bits - 1257 C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); 1258 end 1259 1260 //If this is a write, handle the write by adding the value 1261 // to the linked list, and updating all outputs appropriately 1262 if (WR_EN == 1'b1) begin 1263 if (ideal_full == 1'b1) begin 1264 1265 //If the FIFO is full, do NOT perform the write, 1266 // update flags accordingly 1267 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD 1268 >= C_FIFO_WR_DEPTH) begin 1269 //write unsuccessful - do not change contents 1270 1271 //Do not acknowledge the write 1272 ideal_wr_ack <= 0; 1273 //Reminder that FIFO is still full 1274 ideal_full <= 1'b1; 1275 ideal_almost_full <= 1'b1; 1276 1277 ideal_wr_count <= num_write_words_sized_i; 1278 1279 //If the FIFO is one from full, but reporting full 1280 end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 1281 C_FIFO_WR_DEPTH-1) begin 1282 //No change to FIFO 1283 1284 //Write not successful 1285 ideal_wr_ack <= 0; 1286 //With DEPTH-1 words in the FIFO, it is almost_full 1287 ideal_full <= 1'b0; 1288 ideal_almost_full <= 1'b1; 1289 1290 ideal_wr_count <= num_write_words_sized_i; 1291 1292 1293 //If the FIFO is completely empty, but it is 1294 // reporting FULL for some reason (like reset) 1295 end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= 1296 C_FIFO_WR_DEPTH-2) begin 1297 //No change to FIFO 1298 1299 //Write not successful 1300 ideal_wr_ack <= 0; 1301 //FIFO is really not close to full, so change flag status. 1302 ideal_full <= 1'b0; 1303 ideal_almost_full <= 1'b0; 1304 1305 ideal_wr_count <= num_write_words_sized_i; 1306 end //(tmp_wr_listsize == 0) 1307 1308 end else begin 1309 1310 //If the FIFO is full, do NOT perform the write, 1311 // update flags accordingly 1312 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= 1313 C_FIFO_WR_DEPTH) begin 1314 //write unsuccessful - do not change contents 1315 1316 //Do not acknowledge the write 1317 ideal_wr_ack <= 0; 1318 //Reminder that FIFO is still full 1319 ideal_full <= 1'b1; 1320 ideal_almost_full <= 1'b1; 1321 1322 ideal_wr_count <= num_write_words_sized_i; 1323 1324 //If the FIFO is one from full 1325 end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 1326 C_FIFO_WR_DEPTH-1) begin 1327 //Add value on DIN port to FIFO 1328 write_fifo; 1329 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 1330 1331 //Write successful, so issue acknowledge 1332 // and no error 1333 ideal_wr_ack <= 1; 1334 //This write is CAUSING the FIFO to go full 1335 ideal_full <= 1'b1; 1336 ideal_almost_full <= 1'b1; 1337 1338 ideal_wr_count <= num_write_words_sized_i; 1339 1340 //If the FIFO is 2 from full 1341 end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 1342 C_FIFO_WR_DEPTH-2) begin 1343 //Add value on DIN port to FIFO 1344 write_fifo; 1345 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 1346 //Write successful, so issue acknowledge 1347 // and no error 1348 ideal_wr_ack <= 1; 1349 //Still 2 from full 1350 ideal_full <= 1'b0; 1351 //2 from full, and writing, so set almost_full 1352 ideal_almost_full <= 1'b1; 1353 1354 ideal_wr_count <= num_write_words_sized_i; 1355 1356 //If the FIFO is not close to being full 1357 end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < 1358 C_FIFO_WR_DEPTH-2) begin 1359 //Add value on DIN port to FIFO 1360 write_fifo; 1361 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 1362 //Write successful, so issue acknowledge 1363 // and no error 1364 ideal_wr_ack <= 1; 1365 //Not even close to full. 1366 ideal_full <= 1'b0; 1367 ideal_almost_full <= 1'b0; 1368 1369 ideal_wr_count <= num_write_words_sized_i; 1370 1371 end 1372 1373 end 1374 1375 end else begin //(WR_EN == 1'b1) 1376 1377 //If user did not attempt a write, then do not 1378 // give ack or err 1379 ideal_wr_ack <= 0; 1380 1381 //Implied statements: 1382 //ideal_empty <= ideal_empty; 1383 //ideal_almost_empty <= ideal_almost_empty; 1384 1385 //Check for full 1386 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) 1387 ideal_full <= 1'b1; 1388 else 1389 ideal_full <= 1'b0; 1390 1391 //Check for almost_full 1392 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) 1393 ideal_almost_full <= 1'b1; 1394 else 1395 ideal_almost_full <= 1'b0; 1396 1397 ideal_wr_count <= num_write_words_sized_i; 1398 end 1399 1400 /********************************************************* 1401 * Programmable FULL flags 1402 *********************************************************/ 1403 //Single Programmable Full Constant Threshold 1404 if (C_PROG_FULL_TYPE==1) begin 1405 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1406 prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; 1407 prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; 1408 end else begin 1409 prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; 1410 prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; 1411 end 1412 1413 //Two Programmable Full Constant Thresholds 1414 end else if (C_PROG_FULL_TYPE==2) begin 1415 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1416 prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; 1417 prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; 1418 end else begin 1419 prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; 1420 prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; 1421 end 1422 1423 //Single Programmable Full Threshold Input 1424 end else if (C_PROG_FULL_TYPE==3) begin 1425 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1426 prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; 1427 prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; 1428 end else begin 1429 prog_full_actual_thresh_assert = PROG_FULL_THRESH; 1430 prog_full_actual_thresh_negate = PROG_FULL_THRESH; 1431 end 1432 1433 //Two Programmable Full Threshold Inputs 1434 end else if (C_PROG_FULL_TYPE==4) begin 1435 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1436 prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; 1437 prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; 1438 end else begin 1439 prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; 1440 prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; 1441 end 1442 end //C_PROG_FULL_TYPE 1443 1444 if (num_write_words_pf==0) begin 1445 prog_full_d <= 1'b0; 1446 end else begin 1447 if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 1448 == prog_full_actual_thresh_assert-1) && WR_EN) begin 1449 prog_full_d <= 1'b1; 1450 end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 1451 >= prog_full_actual_thresh_assert) begin 1452 prog_full_d <= 1'b1; 1453 end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 1454 < prog_full_actual_thresh_negate) begin 1455 prog_full_d <= 1'b0; 1456 end 1457 end 1458 1459 if (wr_rst_d1==1 && wr_rst_i==0) begin 1460 ideal_prog_full <= 0; 1461 end else begin 1462 ideal_prog_full <= prog_full_d; 1463 end 1464 num_wr_bits <= next_num_wr_bits; 1465 rd_ptr_wrclk <= rd_ptr; 1466 1467 end //wr_rst_i==0 1468 end // write always 1469 1470 always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r 1471 1472 /****** Reset fifo (case 1)***************************************/ 1473 if (rd_rst_i) begin 1474 num_rd_bits <= 0; 1475 next_num_rd_bits <= 0; 1476 rd_ptr <= C_RD_DEPTH -1; 1477 wr_ptr_rdclk <= C_WR_DEPTH -1; 1478 ideal_dout <= dout_reset_val; 1479 ideal_valid <= 1'b0; 1480 ideal_empty <= 1'b1; 1481 ideal_almost_empty <= 1'b1; 1482 ideal_rd_count <= 0; 1483 1484 ideal_prog_empty <= 1'b1; 1485 prog_empty_d <= 1; 1486 1487 1488 end else begin //rd_rst_i==0 1489 1490 //Determine the current number of words in the FIFO 1491 tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : 1492 num_rd_bits/C_DOUT_WIDTH; 1493 wr_ptr_rdclk_next = wr_ptr; 1494 1495 if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin 1496 next_num_rd_bits = num_rd_bits + 1497 C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH 1498 - wr_ptr_rdclk_next); 1499 end else begin 1500 next_num_rd_bits = num_rd_bits + 1501 C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); 1502 end 1503 1504 /*****************************************************************/ 1505 // Read Operation - Read Latency 1 1506 /*****************************************************************/ 1507 if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin 1508 1509 if (RD_EN == 1'b1) begin 1510 1511 if (ideal_empty == 1'b1) begin 1512 1513 //If the FIFO is completely empty, and is reporting empty 1514 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 1515 begin 1516 //Do not change the contents of the FIFO 1517 1518 //Do not acknowledge the read from empty FIFO 1519 ideal_valid <= 1'b0; 1520 //Reminder that FIFO is still empty 1521 ideal_empty <= 1'b1; 1522 ideal_almost_empty <= 1'b1; 1523 1524 ideal_rd_count <= num_read_words_sized_i; 1525 end // if (tmp_rd_listsize <= 0) 1526 1527 //If the FIFO is one from empty, but it is reporting empty 1528 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) 1529 begin 1530 //Do not change the contents of the FIFO 1531 1532 //Do not acknowledge the read from empty FIFO 1533 ideal_valid <= 1'b0; 1534 //Note that FIFO is no longer empty, but is almost empty (has one word left) 1535 ideal_empty <= 1'b0; 1536 ideal_almost_empty <= 1'b1; 1537 1538 ideal_rd_count <= num_read_words_sized_i; 1539 1540 end // if (tmp_rd_listsize == 1) 1541 1542 //If the FIFO is two from empty, and is reporting empty 1543 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) 1544 begin 1545 //Do not change the contents of the FIFO 1546 1547 //Do not acknowledge the read from empty FIFO 1548 ideal_valid <= 1'b0; 1549 //Fifo has two words, so is neither empty or almost empty 1550 ideal_empty <= 1'b0; 1551 ideal_almost_empty <= 1'b0; 1552 1553 ideal_rd_count <= num_read_words_sized_i; 1554 1555 end // if (tmp_rd_listsize == 2) 1556 1557 //If the FIFO is not close to empty, but is reporting that it is 1558 // Treat the FIFO as empty this time, but unset EMPTY flags. 1559 if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) 1560 begin 1561 //Do not change the contents of the FIFO 1562 1563 //Do not acknowledge the read from empty FIFO 1564 ideal_valid <= 1'b0; 1565 //Note that the FIFO is No Longer Empty or Almost Empty 1566 ideal_empty <= 1'b0; 1567 ideal_almost_empty <= 1'b0; 1568 1569 ideal_rd_count <= num_read_words_sized_i; 1570 1571 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 1572 end // else: if(ideal_empty == 1'b1) 1573 1574 else //if (ideal_empty == 1'b0) 1575 begin 1576 1577 //If the FIFO is completely full, and we are successfully reading from it 1578 if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) 1579 begin 1580 //Read the value from the FIFO 1581 read_fifo; 1582 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1583 1584 //Acknowledge the read from the FIFO, no error 1585 ideal_valid <= 1'b1; 1586 //Not close to empty 1587 ideal_empty <= 1'b0; 1588 ideal_almost_empty <= 1'b0; 1589 1590 ideal_rd_count <= num_read_words_sized_i; 1591 1592 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) 1593 1594 //If the FIFO is not close to being empty 1595 else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) 1596 begin 1597 //Read the value from the FIFO 1598 read_fifo; 1599 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1600 1601 //Acknowledge the read from the FIFO, no error 1602 ideal_valid <= 1'b1; 1603 //Not close to empty 1604 ideal_empty <= 1'b0; 1605 ideal_almost_empty <= 1'b0; 1606 1607 ideal_rd_count <= num_read_words_sized_i; 1608 1609 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 1610 1611 //If the FIFO is two from empty 1612 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) 1613 begin 1614 //Read the value from the FIFO 1615 read_fifo; 1616 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1617 1618 //Acknowledge the read from the FIFO, no error 1619 ideal_valid <= 1'b1; 1620 //Fifo is not yet empty. It is going almost_empty 1621 ideal_empty <= 1'b0; 1622 ideal_almost_empty <= 1'b1; 1623 1624 ideal_rd_count <= num_read_words_sized_i; 1625 1626 end // if (tmp_rd_listsize == 2) 1627 1628 //If the FIFO is one from empty 1629 else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) 1630 begin 1631 //Read the value from the FIFO 1632 read_fifo; 1633 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1634 1635 //Acknowledge the read from the FIFO, no error 1636 ideal_valid <= 1'b1; 1637 //Note that FIFO is GOING empty 1638 ideal_empty <= 1'b1; 1639 ideal_almost_empty <= 1'b1; 1640 1641 ideal_rd_count <= num_read_words_sized_i; 1642 1643 end // if (tmp_rd_listsize == 1) 1644 1645 1646 //If the FIFO is completely empty 1647 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 1648 begin 1649 //Do not change the contents of the FIFO 1650 1651 //Do not acknowledge the read from empty FIFO 1652 ideal_valid <= 1'b0; 1653 //Reminder that FIFO is still empty 1654 ideal_empty <= 1'b1; 1655 ideal_almost_empty <= 1'b1; 1656 1657 ideal_rd_count <= num_read_words_sized_i; 1658 1659 end // if (tmp_rd_listsize <= 0) 1660 1661 end // if (ideal_empty == 1'b0) 1662 1663 end //(RD_EN == 1'b1) 1664 1665 else //if (RD_EN == 1'b0) 1666 begin 1667 //If user did not attempt a read, do not give an ack or err 1668 ideal_valid <= 1'b0; 1669 1670 //Check for empty 1671 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 1672 ideal_empty <= 1'b1; 1673 else 1674 ideal_empty <= 1'b0; 1675 1676 //Check for almost_empty 1677 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) 1678 ideal_almost_empty <= 1'b1; 1679 else 1680 ideal_almost_empty <= 1'b0; 1681 1682 ideal_rd_count <= num_read_words_sized_i; 1683 1684 end // else: !if(RD_EN == 1'b1) 1685 1686 /*****************************************************************/ 1687 // Read Operation - Read Latency 0 1688 /*****************************************************************/ 1689 end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1690 if (RD_EN == 1'b1) begin 1691 1692 if (ideal_empty == 1'b1) begin 1693 1694 //If the FIFO is completely empty, and is reporting empty 1695 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin 1696 //Do not change the contents of the FIFO 1697 1698 //Do not acknowledge the read from empty FIFO 1699 ideal_valid <= 1'b0; 1700 //Reminder that FIFO is still empty 1701 ideal_empty <= 1'b1; 1702 ideal_almost_empty <= 1'b1; 1703 1704 ideal_rd_count <= num_read_words_sized_i; 1705 1706 //If the FIFO is one from empty, but it is reporting empty 1707 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin 1708 //Do not change the contents of the FIFO 1709 1710 //Do not acknowledge the read from empty FIFO 1711 ideal_valid <= 1'b0; 1712 //Note that FIFO is no longer empty, but is almost empty (has one word left) 1713 ideal_empty <= 1'b0; 1714 ideal_almost_empty <= 1'b1; 1715 1716 ideal_rd_count <= num_read_words_sized_i; 1717 1718 //If the FIFO is two from empty, and is reporting empty 1719 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin 1720 //Do not change the contents of the FIFO 1721 1722 //Do not acknowledge the read from empty FIFO 1723 ideal_valid <= 1'b0; 1724 //Fifo has two words, so is neither empty or almost empty 1725 ideal_empty <= 1'b0; 1726 ideal_almost_empty <= 1'b0; 1727 1728 ideal_rd_count <= num_read_words_sized_i; 1729 1730 //If the FIFO is not close to empty, but is reporting that it is 1731 // Treat the FIFO as empty this time, but unset EMPTY flags. 1732 end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && 1733 (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin 1734 //Do not change the contents of the FIFO 1735 1736 //Do not acknowledge the read from empty FIFO 1737 ideal_valid <= 1'b0; 1738 //Note that the FIFO is No Longer Empty or Almost Empty 1739 ideal_empty <= 1'b0; 1740 ideal_almost_empty <= 1'b0; 1741 1742 ideal_rd_count <= num_read_words_sized_i; 1743 1744 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 1745 1746 end else begin 1747 1748 //If the FIFO is completely full, and we are successfully reading from it 1749 if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin 1750 //Read the value from the FIFO 1751 read_fifo; 1752 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1753 1754 //Acknowledge the read from the FIFO, no error 1755 ideal_valid <= 1'b1; 1756 //Not close to empty 1757 ideal_empty <= 1'b0; 1758 ideal_almost_empty <= 1'b0; 1759 1760 ideal_rd_count <= num_read_words_sized_i; 1761 1762 //If the FIFO is not close to being empty 1763 end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && 1764 (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin 1765 //Read the value from the FIFO 1766 read_fifo; 1767 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1768 1769 //Acknowledge the read from the FIFO, no error 1770 ideal_valid <= 1'b1; 1771 //Not close to empty 1772 ideal_empty <= 1'b0; 1773 ideal_almost_empty <= 1'b0; 1774 1775 ideal_rd_count <= num_read_words_sized_i; 1776 1777 //If the FIFO is two from empty 1778 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin 1779 //Read the value from the FIFO 1780 read_fifo; 1781 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1782 1783 //Acknowledge the read from the FIFO, no error 1784 ideal_valid <= 1'b1; 1785 //Fifo is not yet empty. It is going almost_empty 1786 ideal_empty <= 1'b0; 1787 ideal_almost_empty <= 1'b1; 1788 1789 ideal_rd_count <= num_read_words_sized_i; 1790 1791 //If the FIFO is one from empty 1792 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin 1793 //Read the value from the FIFO 1794 read_fifo; 1795 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 1796 1797 //Acknowledge the read from the FIFO, no error 1798 ideal_valid <= 1'b1; 1799 //Note that FIFO is GOING empty 1800 ideal_empty <= 1'b1; 1801 ideal_almost_empty <= 1'b1; 1802 1803 ideal_rd_count <= num_read_words_sized_i; 1804 1805 //If the FIFO is completely empty 1806 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin 1807 //Do not change the contents of the FIFO 1808 1809 //Do not acknowledge the read from empty FIFO 1810 ideal_valid <= 1'b0; 1811 //Reminder that FIFO is still empty 1812 ideal_empty <= 1'b1; 1813 ideal_almost_empty <= 1'b1; 1814 1815 ideal_rd_count <= num_read_words_sized_i; 1816 1817 end // if (tmp_rd_listsize <= 0) 1818 1819 end // if (ideal_empty == 1'b0) 1820 1821 end else begin//(RD_EN == 1'b0) 1822 1823 1824 //If user did not attempt a read, do not give an ack or err 1825 ideal_valid <= 1'b0; 1826 1827 //Check for empty 1828 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 1829 ideal_empty <= 1'b1; 1830 else 1831 ideal_empty <= 1'b0; 1832 1833 //Check for almost_empty 1834 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) 1835 ideal_almost_empty <= 1'b1; 1836 else 1837 ideal_almost_empty <= 1'b0; 1838 1839 ideal_rd_count <= num_read_words_sized_i; 1840 1841 end // else: !if(RD_EN == 1'b1) 1842 end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 1843 1844 1845 /********************************************************* 1846 * Programmable EMPTY flags 1847 *********************************************************/ 1848 //Determine the Assert and Negate thresholds for Programmable Empty 1849 // (Subtract 2 read-sized words when using Preload 0) 1850 1851 //Single Programmable Empty Constant Threshold 1852 if (C_PROG_EMPTY_TYPE==1) begin 1853 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1854 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; 1855 prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; 1856 end 1857 else begin 1858 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; 1859 prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; 1860 end 1861 1862 //Two Programmable Empty Constant Thresholds 1863 end else if (C_PROG_EMPTY_TYPE==2) begin 1864 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1865 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; 1866 prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; 1867 end 1868 else begin 1869 prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; 1870 prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; 1871 end 1872 1873 //Single Programmable Empty Constant Threshold 1874 end else if (C_PROG_EMPTY_TYPE==3) begin 1875 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1876 prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; 1877 prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; 1878 end 1879 else begin 1880 prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; 1881 prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; 1882 1883 end 1884 //Two Programmable Empty Constant Thresholds 1885 end else if (C_PROG_EMPTY_TYPE==4) begin 1886 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 1887 prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; 1888 prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; 1889 end 1890 else begin 1891 prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; 1892 prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; 1893 end 1894 end 1895 1896 if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) 1897 && RD_EN) begin 1898 prog_empty_d <= 1'b1; 1899 end else if (num_read_words_pe/C_DEPTH_RATIO_WR 1900 <= prog_empty_actual_thresh_assert) begin 1901 prog_empty_d <= 1'b1; 1902 end else if (num_read_words_pe/C_DEPTH_RATIO_WR 1903 > prog_empty_actual_thresh_negate) begin 1904 prog_empty_d <= 1'b0; 1905 end 1906 1907 1908 ideal_prog_empty <= prog_empty_d; 1909 num_rd_bits <= next_num_rd_bits; 1910 wr_ptr_rdclk <= wr_ptr; 1911 end //rd_rst_i==0 1912 end //always 1913 1914endmodule // fifo_generator_v4_3_bhv_ver_as 1915 1916 1917/******************************************************************************* 1918 * Declaration of top-level module 1919 ******************************************************************************/ 1920module fifo_generator_v4_3_bhv_ver_ss 1921 ( 1922 CLK, RST, SRST, DIN, WR_EN, RD_EN, 1923 PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, 1924 PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, 1925 DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, 1926 ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, 1927 PROG_FULL, PROG_EMPTY 1928 ); 1929 1930/****************************************************************************** 1931 * Declare user parameters and their defaults 1932 *****************************************************************************/ 1933 parameter C_COMMON_CLOCK = 0; 1934 parameter C_COUNT_TYPE = 0; 1935 parameter C_DATA_COUNT_WIDTH = 2; 1936 parameter C_DEFAULT_VALUE = ""; 1937 parameter C_DIN_WIDTH = 8; 1938 parameter C_DOUT_RST_VAL = ""; 1939 parameter C_DOUT_WIDTH = 8; 1940 parameter C_ENABLE_RLOCS = 0; 1941 parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model 1942 parameter C_HAS_ALMOST_EMPTY = 0; 1943 parameter C_HAS_ALMOST_FULL = 0; 1944 parameter C_HAS_BACKUP = 0; 1945 parameter C_HAS_DATA_COUNT = 0; 1946 parameter C_HAS_MEMINIT_FILE = 0; 1947 parameter C_HAS_OVERFLOW = 0; 1948 parameter C_HAS_RD_DATA_COUNT = 0; 1949 parameter C_HAS_RD_RST = 0; 1950 parameter C_HAS_RST = 0; 1951 parameter C_HAS_SRST = 0; 1952 parameter C_HAS_UNDERFLOW = 0; 1953 parameter C_HAS_VALID = 0; 1954 parameter C_HAS_WR_ACK = 0; 1955 parameter C_HAS_WR_DATA_COUNT = 0; 1956 parameter C_HAS_WR_RST = 0; 1957 parameter C_IMPLEMENTATION_TYPE = 0; 1958 parameter C_INIT_WR_PNTR_VAL = 0; 1959 parameter C_MEMORY_TYPE = 1; 1960 parameter C_MIF_FILE_NAME = ""; 1961 parameter C_OPTIMIZATION_MODE = 0; 1962 parameter C_OVERFLOW_LOW = 0; 1963 parameter C_PRELOAD_LATENCY = 1; 1964 parameter C_PRELOAD_REGS = 0; 1965 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; 1966 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; 1967 parameter C_PROG_EMPTY_TYPE = 0; 1968 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; 1969 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; 1970 parameter C_PROG_FULL_TYPE = 0; 1971 parameter C_RD_DATA_COUNT_WIDTH = 2; 1972 parameter C_RD_DEPTH = 256; 1973 parameter C_RD_PNTR_WIDTH = 8; 1974 parameter C_UNDERFLOW_LOW = 0; 1975 parameter C_VALID_LOW = 0; 1976 parameter C_WR_ACK_LOW = 0; 1977 parameter C_WR_DATA_COUNT_WIDTH = 2; 1978 parameter C_WR_DEPTH = 256; 1979 parameter C_WR_PNTR_WIDTH = 8; 1980 parameter C_WR_RESPONSE_LATENCY = 1; 1981 parameter C_FULL_FLAGS_RST_VAL = 1; 1982 parameter C_USE_EMBEDDED_REG = 0; 1983 1984 1985/****************************************************************************** 1986 * Declare Input and Output Ports 1987 *****************************************************************************/ 1988 input CLK; 1989 input [C_DIN_WIDTH-1:0] DIN; 1990 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; 1991 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; 1992 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; 1993 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; 1994 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; 1995 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; 1996 input RD_EN; 1997 input RST; 1998 input SRST; 1999 input WR_EN; 2000 output ALMOST_EMPTY; 2001 output ALMOST_FULL; 2002 output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; 2003 output [C_DOUT_WIDTH-1:0] DOUT; 2004 output EMPTY; 2005 output FULL; 2006 output OVERFLOW; 2007 output PROG_EMPTY; 2008 output PROG_FULL; 2009 output VALID; 2010 output UNDERFLOW; 2011 output WR_ACK; 2012 2013/******************************************************************************* 2014 * Input and output register declarations 2015 ******************************************************************************/ 2016/******************************************************************************* 2017 * Parameters used as constants 2018 ******************************************************************************/ 2019 //When RST is present, set FULL reset value to '1'. 2020 //If core has no RST, make sure FULL powers-on as '0'. 2021 //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not 2022 //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. 2023 // Therefore, during SRST, all the FULL flags reset to 0. 2024 parameter C_HAS_FAST_FIFO = 0; 2025 parameter C_FIFO_WR_DEPTH = (C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; 2026 parameter C_FIFO_RD_DEPTH = (C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; 2027 2028 /**************************************************************************** 2029 * Internal Registers and wires 2030 ***************************************************************************/ 2031 wire wr_ack_i; 2032 wire overflow_i; 2033 wire underflow_i; 2034 wire valid_i; 2035 wire valid_out; 2036 reg valid_d1; 2037 wire srst_i; 2038 /******************************************************************************* 2039 * Internal registers and wires for internal reset logics 2040 ******************************************************************************/ 2041 reg rst_asreg =0; 2042 reg rst_asreg_d1 =0; 2043 reg rst_asreg_d2 =0; 2044 reg rst_reg =0; 2045 reg rst_d1 =0; 2046 wire rst_comb; 2047 wire rst_i; 2048 2049 2050 //Memory which will be used to simulate a FIFO 2051 reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; 2052 reg [31:0] num_bits; 2053 reg [31:0] wr_ptr; 2054 reg [31:0] rd_ptr; 2055 wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; 2056 reg [31:0] num_read_words_q; 2057 wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; 2058 reg [31:0] num_write_words_q; 2059 //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle. 2060 //reg [3:0] power_on_timer; 2061 2062 //Special ideal FIFO signals 2063 reg [C_DOUT_WIDTH-1:0] ideal_dout; 2064 reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; 2065 wire [C_DOUT_WIDTH-1:0] ideal_dout_out; 2066 reg ideal_wr_ack; 2067 reg ideal_valid; 2068 reg ideal_overflow; 2069 reg ideal_underflow; 2070 reg ideal_full; 2071 reg ideal_empty; 2072 reg ideal_almost_full; 2073 reg ideal_almost_empty; 2074 reg ideal_prog_full; 2075 reg ideal_prog_empty; 2076 2077 2078 //MSBs of the counts 2079 wire [C_DATA_COUNT_WIDTH-1:0] ideal_d_count; 2080 2081 //user specified value for reseting the size of the fifo 2082 reg [C_DOUT_WIDTH-1:0] dout_reset_val; 2083 2084 2085 //temporary registers for WR_RESPONSE_LATENCY feature 2086 reg ideal_wr_ack_q; 2087 reg ideal_overflow_q; 2088 2089 reg prog_full_d; 2090 reg prog_empty_d; 2091 2092 //Delayed version of RST 2093 reg rst_q; 2094 reg rst_qq; 2095 2096 /**************************************************************************** 2097 * Function Declarations 2098 ***************************************************************************/ 2099 task write_fifo; 2100 begin 2101 memory[wr_ptr] <= DIN; 2102 if (wr_ptr == 0) begin 2103 wr_ptr <= C_WR_DEPTH - 1; 2104 end else begin 2105 wr_ptr <= wr_ptr - 1; 2106 end 2107 end 2108 endtask // write_fifo 2109 2110 task read_fifo; 2111 begin 2112 ideal_dout <= memory[rd_ptr]; 2113 if (rd_ptr == 0) begin 2114 rd_ptr <= C_RD_DEPTH - 1; 2115 end else begin 2116 rd_ptr <= rd_ptr - 1; 2117 end 2118 end 2119 endtask 2120 2121 /**************************************************************************** 2122 * log2_val 2123 * Returns the 'log2' value for the input value for the supported ratios 2124 ***************************************************************************/ 2125 function [31:0] log2_val; 2126 input [31:0] binary_val; 2127 2128 begin 2129 if (binary_val == 8) begin 2130 log2_val = 3; 2131 end else if (binary_val == 4) begin 2132 log2_val = 2; 2133 end else begin 2134 log2_val = 1; 2135 end 2136 end 2137 endfunction 2138 2139 /**************************************************************************** 2140 * hexstr_conv 2141 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 2142 ***************************************************************************/ 2143 function [C_DOUT_WIDTH-1:0] hexstr_conv; 2144 input [(C_DOUT_WIDTH*8)-1:0] def_data; 2145 2146 integer index,i,j; 2147 reg [3:0] bin; 2148 2149 begin 2150 index = 0; 2151 hexstr_conv = 'b0; 2152 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 2153 begin 2154 case (def_data[7:0]) 2155 8'b00000000 : 2156 begin 2157 bin = 4'b0000; 2158 i = -1; 2159 end 2160 8'b00110000 : bin = 4'b0000; 2161 8'b00110001 : bin = 4'b0001; 2162 8'b00110010 : bin = 4'b0010; 2163 8'b00110011 : bin = 4'b0011; 2164 8'b00110100 : bin = 4'b0100; 2165 8'b00110101 : bin = 4'b0101; 2166 8'b00110110 : bin = 4'b0110; 2167 8'b00110111 : bin = 4'b0111; 2168 8'b00111000 : bin = 4'b1000; 2169 8'b00111001 : bin = 4'b1001; 2170 8'b01000001 : bin = 4'b1010; 2171 8'b01000010 : bin = 4'b1011; 2172 8'b01000011 : bin = 4'b1100; 2173 8'b01000100 : bin = 4'b1101; 2174 8'b01000101 : bin = 4'b1110; 2175 8'b01000110 : bin = 4'b1111; 2176 8'b01100001 : bin = 4'b1010; 2177 8'b01100010 : bin = 4'b1011; 2178 8'b01100011 : bin = 4'b1100; 2179 8'b01100100 : bin = 4'b1101; 2180 8'b01100101 : bin = 4'b1110; 2181 8'b01100110 : bin = 4'b1111; 2182 default : 2183 begin 2184 bin = 4'bx; 2185 end 2186 endcase 2187 for( j=0; j<4; j=j+1) 2188 begin 2189 if ((index*4)+j < C_DOUT_WIDTH) 2190 begin 2191 hexstr_conv[(index*4)+j] = bin[j]; 2192 end 2193 end 2194 index = index + 1; 2195 def_data = def_data >> 8; 2196 end 2197 end 2198 endfunction 2199 2200 /***************************************************************************** 2201 * Initialize Signals 2202 ****************************************************************************/ 2203 initial begin 2204 num_bits = 0; 2205 num_read_words_q = 0; 2206 num_write_words_q = 0; 2207 rd_ptr = C_RD_DEPTH -1; 2208 wr_ptr = C_WR_DEPTH -1; 2209 dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); 2210 ideal_dout = dout_reset_val; 2211 ideal_wr_ack = 1'b0; 2212 ideal_valid = 1'b0; 2213 valid_d1 = 1'b0; 2214 ideal_overflow = 1'b0; 2215 ideal_underflow = 1'b0; 2216 //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) 2217 //ideal_full = C_FULL_RESET_VAL; //was in v3.1 2218 ideal_full = 1'b0; //v3.2 2219 ideal_empty = 1'b1; 2220 //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) 2221 //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 2222 ideal_almost_full = 1'b0; 2223 ideal_almost_empty = 1'b1; 2224 //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) 2225 //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 2226 ideal_prog_full = 1'b0; //v3.2 2227 ideal_prog_empty = 1'b1; 2228 2229 //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) 2230 //Therefore, prog_full_d is also changed 2231 //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 2232 prog_full_d = 1'b0; //v3.2 2233 prog_empty_d = 1'b1; 2234 2235 //Removed in v3.2 2236 //power_on_timer = C_HAS_RST ? 4'h3 : 4'h0; 2237 2238 //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core. 2239 rst_q = 1'b0; 2240 rst_qq = 1'b0; 2241 end 2242 2243 2244 /***************************************************************************** 2245 * Assign Internal ideal signals to output ports 2246 ****************************************************************************/ 2247 assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && 2248 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 2249 ideal_dout_d1: ideal_dout; 2250 assign DOUT = ideal_dout_out; 2251 //was in v3.1 2252 //assign FULL = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full; 2253 //v3.2 2254 assign FULL = ideal_full; 2255 2256 assign EMPTY = ideal_empty; 2257 //was in v3.1 2258 //assign ALMOST_FULL = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full; 2259 //v3.2 2260 assign ALMOST_FULL = ideal_almost_full; 2261 2262 assign ALMOST_EMPTY = ideal_almost_empty; 2263 2264 assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; 2265 assign DATA_COUNT = ideal_d_count; 2266 2267 //was in v3.1 2268 //assign PROG_FULL = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full; 2269 //v3.2 2270 assign PROG_FULL = ideal_prog_full; 2271 2272 assign PROG_EMPTY = ideal_prog_empty; 2273 2274 //Handshaking signals can be active low, depending on _LOW parameters 2275 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; 2276 assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; 2277 assign valid_out = (C_PRELOAD_LATENCY==2 && 2278 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 2279 valid_d1: valid_i; 2280 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; 2281 assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; 2282 2283 assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; 2284 assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : 2285 (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : 2286 (WR_EN & !FULL); 2287 assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; 2288 assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : 2289 (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : 2290 (WR_EN & FULL); 2291 2292 assign srst_i = C_HAS_SRST ? SRST : 0; 2293 2294 /******************************************************************************* 2295 * Internal reset logics 2296 ******************************************************************************/ 2297 assign rst_comb = !rst_asreg_d2 && rst_asreg; 2298 assign rst_i = C_HAS_RST ? rst_reg : 0; 2299 2300 always @(posedge CLK or posedge rst_i) begin 2301 if (rst_i == 1'b1) begin 2302 valid_d1 <= 1'b0; 2303 end else begin 2304 if (srst_i) begin 2305 valid_d1 <= 1'b0; 2306 end else begin 2307 valid_d1 <= valid_i; 2308 end 2309 end 2310 end 2311 always @(posedge CLK or posedge rst_i) begin 2312 if (rst_i == 1'b1) begin 2313 ideal_dout_d1 <= dout_reset_val; 2314 end else begin 2315 if (srst_i) begin 2316 ideal_dout_d1 <= dout_reset_val; 2317 end else begin 2318 ideal_dout_d1 <= ideal_dout; 2319 end 2320 end 2321 end 2322 2323 always @(posedge CLK or posedge RST) begin 2324 if (RST == 1'b1) begin 2325 rst_asreg <= 1'b1; 2326 end else begin 2327 if (rst_asreg_d1 == 1'b1) begin 2328 rst_asreg <= 1'b0; 2329 end else begin 2330 rst_asreg <= rst_asreg; 2331 end 2332 end 2333 end 2334 2335 always @(posedge CLK) begin 2336 rst_asreg_d1 <= rst_asreg; 2337 rst_asreg_d2 <= rst_asreg_d1; 2338 end 2339 2340 always @(posedge CLK or posedge rst_comb) begin 2341 if (rst_comb == 1'b1) begin 2342 rst_reg <= 1'b1; 2343 end else begin 2344 rst_reg <= 1'b0; 2345 end 2346 end 2347 2348 2349 /******************************************************************************* 2350 * Write and Read Logics 2351 ******************************************************************************/ 2352 2353 always @(posedge CLK or posedge rst_i) 2354 begin : gen_wr_ack_resp 2355 2356 //Register reset 2357 rst_q <= rst_i; 2358 rst_qq <= rst_q; 2359 2360 //Register output signals to achieve desired WR_RESPONSE latency 2361 if (C_WR_RESPONSE_LATENCY == 2) begin 2362 if (rst_i == 1) begin 2363 ideal_wr_ack_q <= 0; 2364 ideal_overflow_q <= 0; 2365 end else begin 2366 ideal_wr_ack_q <= ideal_wr_ack; 2367 ideal_overflow_q <= ideal_overflow; 2368 end 2369 end 2370 2371 //Removed in v3.2 2372 /* 2373 if (rst_i == 1) begin 2374 power_on_timer <= 0; 2375 end else if (power_on_timer > 0) begin 2376 power_on_timer <= power_on_timer -1; 2377 end else begin 2378 power_on_timer <= 0; 2379 end 2380 */ 2381 end // block: gen_wr_ack_resp 2382 2383 // block memory has a synchronous reset 2384 always @(posedge CLK) begin : gen_fifo_blkmemdout 2385 //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. 2386 //if (rst_i || rst_q || rst_qq) begin //was in v3.1 2387 if (rst_i || rst_q || srst_i) begin //v3.2 2388 /******Initialize Read Domain Signals************************************/ 2389 if (C_MEMORY_TYPE == 1) begin 2390 ideal_dout <= dout_reset_val; 2391 end 2392 //v3.2 2393 //end else begin 2394 //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1 2395 // if (C_MEMORY_TYPE == 1) begin //v3.2 2396 // ideal_dout <= dout_reset_val; 2397 // end 2398 end 2399 end 2400 2401 always @(posedge CLK or posedge rst_i) begin : gen_fifo 2402 2403 /****** Reset fifo - Asynchronous Reset*************************************/ 2404 //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. 2405 //if (rst_i || rst_q || rst_qq) begin //was in v3.1 2406 //if (rst_i || rst_q) begin //v3.2 2407 if (rst_i ) begin //v3.2 2408 /******Initialize Generic FIFO constructs********************************/ 2409 num_bits <= 0; 2410 wr_ptr <= C_WR_DEPTH - 1; 2411 rd_ptr <= C_RD_DEPTH - 1; 2412 num_read_words_q <= 0; 2413 num_write_words_q <= 0; 2414 2415 2416 /******Initialize Write Domain Signals***********************************/ 2417 ideal_wr_ack <= 0; 2418 ideal_full <= C_FULL_FLAGS_RST_VAL; 2419 ideal_almost_full <= C_FULL_FLAGS_RST_VAL; 2420 2421 /******Initialize Read Domain Signals************************************/ 2422 if (C_MEMORY_TYPE != 1) begin 2423 ideal_dout <= dout_reset_val; 2424 end 2425 ideal_valid <= 1'b0; 2426 ideal_empty <= 1'b1; 2427 ideal_almost_empty <= 1'b1; 2428 2429 end else begin 2430 if (srst_i) begin 2431 // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. 2432 if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin 2433 /******Initialize Generic FIFO constructs********************************/ 2434 num_bits <= 0; 2435 wr_ptr <= C_WR_DEPTH - 1; 2436 rd_ptr <= C_RD_DEPTH - 1; 2437 num_read_words_q <= 0; 2438 num_write_words_q <= 0; 2439 2440 /******Initialize Write Domain Signals***********************************/ 2441 ideal_wr_ack <= 0; 2442 ideal_full <= 0; //'0' 2443 ideal_almost_full <= 0; //'0' 2444 2445 /******Initialize Read Domain Signals************************************/ 2446 //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block. 2447 if (C_MEMORY_TYPE == 2) begin 2448 ideal_dout <= dout_reset_val; 2449 end 2450 ideal_valid <= 1'b0; 2451 ideal_empty <= 1'b1; 2452 ideal_almost_empty <= 1'b1; 2453 end 2454 2455 end else begin //normal operating conditions 2456 /**********************************************************************/ 2457 // Synchronous FIFO Condition #1 : Writing and not reading 2458 /**********************************************************************/ 2459 if (WR_EN & ~RD_EN) begin 2460 2461 /*********************************/ 2462 //If the FIFO is full, do NOT perform the write, 2463 // update flags accordingly 2464 /*********************************/ 2465 if (num_write_words >= C_FIFO_WR_DEPTH) begin 2466 ideal_wr_ack <= 0; 2467 2468 //still full 2469 ideal_full <= 1'b1; 2470 ideal_almost_full <= 1'b1; 2471 2472 //write unsuccessful - do not change contents 2473 2474 // no read attempted 2475 ideal_valid <= 1'b0; 2476 2477 //Not near empty 2478 ideal_empty <= 1'b0; 2479 ideal_almost_empty <= 1'b0; 2480 2481 2482 /*********************************/ 2483 //If the FIFO is reporting FULL 2484 // (Startup condition) 2485 /*********************************/ 2486 end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin 2487 ideal_wr_ack <= 0; 2488 2489 //still full 2490 ideal_full <= 1'b0; 2491 ideal_almost_full <= 1'b0; 2492 2493 //write unsuccessful - do not change contents 2494 2495 // no read attempted 2496 ideal_valid <= 1'b0; 2497 2498 //FIFO EMPTY in this state can not be determined 2499 //ideal_empty <= 1'b0; 2500 //ideal_almost_empty <= 1'b0; 2501 2502 2503 /*********************************/ 2504 //If the FIFO is one from full 2505 /*********************************/ 2506 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 2507 //good write 2508 ideal_wr_ack <= 1; 2509 2510 //FIFO is one from FULL and going FULL 2511 ideal_full <= 1'b1; 2512 ideal_almost_full <= 1'b1; 2513 2514 //Add input data 2515 write_fifo; 2516 2517 // no read attempted 2518 ideal_valid <= 1'b0; 2519 2520 //Not near empty 2521 ideal_empty <= 1'b0; 2522 ideal_almost_empty <= 1'b0; 2523 2524 num_bits <= num_bits + C_DIN_WIDTH; 2525 2526 /*********************************/ 2527 //If the FIFO is 2 from full 2528 /*********************************/ 2529 end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin 2530 //good write 2531 ideal_wr_ack <= 1; 2532 2533 //2 from full, and writing, so set almost_full 2534 ideal_full <= 1'b0; 2535 ideal_almost_full <= 1'b1; 2536 2537 //Add input data 2538 write_fifo; 2539 2540 //no read attempted 2541 ideal_valid <= 1'b0; 2542 2543 //Not near empty 2544 ideal_empty <= 1'b0; 2545 ideal_almost_empty <= 1'b0; 2546 2547 num_bits <= num_bits + C_DIN_WIDTH; 2548 2549 /*********************************/ 2550 //If the FIFO is ALMOST EMPTY 2551 /*********************************/ 2552 end else if (num_read_words == 1) begin 2553 //good write 2554 ideal_wr_ack <= 1; 2555 2556 //Not near FULL 2557 ideal_full <= 1'b0; 2558 ideal_almost_full <= 1'b0; 2559 2560 //Add input data 2561 write_fifo; 2562 2563 // no read attempted 2564 ideal_valid <= 1'b0; 2565 2566 //Leaving ALMOST_EMPTY 2567 ideal_empty <= 1'b0; 2568 ideal_almost_empty <= 1'b0; 2569 2570 num_bits <= num_bits + C_DIN_WIDTH; 2571 2572 /*********************************/ 2573 //If the FIFO is EMPTY 2574 /*********************************/ 2575 end else if (num_read_words == 0) begin 2576 // good write 2577 ideal_wr_ack <= 1; 2578 2579 //Not near FULL 2580 ideal_full <= 1'b0; 2581 ideal_almost_full <= 1'b0; 2582 2583 //Add input data 2584 write_fifo; 2585 2586 // no read attempted 2587 ideal_valid <= 1'b0; 2588 2589 //Leaving EMPTY (still ALMOST_EMPTY) 2590 ideal_empty <= 1'b0; 2591 ideal_almost_empty <= 1'b1; 2592 2593 num_bits <= num_bits + C_DIN_WIDTH; 2594 2595 /*********************************/ 2596 //If the FIFO is not near EMPTY or FULL 2597 /*********************************/ 2598 end else begin 2599 // good write 2600 ideal_wr_ack <= 1; 2601 2602 //Not near FULL 2603 ideal_full <= 1'b0; 2604 ideal_almost_full <= 1'b0; 2605 2606 //Add input data 2607 write_fifo; 2608 2609 // no read attempted 2610 ideal_valid <= 1'b0; 2611 2612 //Not near EMPTY 2613 ideal_empty <= 1'b0; 2614 ideal_almost_empty <= 1'b0; 2615 2616 num_bits <= num_bits + C_DIN_WIDTH; 2617 2618 end // average case 2619 2620 2621 /**********************************************************************/ 2622 // Synchronous FIFO Condition #2 : Reading and not writing 2623 /**********************************************************************/ 2624 end else if (~WR_EN & RD_EN) begin 2625 2626 /*********************************/ 2627 //If the FIFO is EMPTY 2628 /*********************************/ 2629 if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin 2630 //no write attemped 2631 ideal_wr_ack <= 0; 2632 2633 //FIFO is not near FULL 2634 ideal_full <= 1'b0; 2635 ideal_almost_full <= 1'b0; 2636 2637 //Read will fail 2638 ideal_valid <= 1'b0; 2639 2640 //FIFO is still empty 2641 ideal_empty <= 1'b1; 2642 ideal_almost_empty <= 1'b1; 2643 2644 //No read 2645 2646 /*********************************/ 2647 //If the FIFO is ALMOST EMPTY 2648 /*********************************/ 2649 end else if (num_read_words == 1) begin 2650 //no write attempted 2651 ideal_wr_ack <= 0; 2652 2653 //FIFO is not near FULL 2654 ideal_full <= 1'b0; 2655 ideal_almost_full <= 1'b0; 2656 2657 //Read successful 2658 ideal_valid <= 1'b1; 2659 2660 //This read will make FIFO go empty 2661 ideal_empty <= 1'b1; 2662 ideal_almost_empty <= 1'b1; 2663 2664 //Get the data from the FIFO 2665 read_fifo; 2666 num_bits <= num_bits - C_DIN_WIDTH; 2667 2668 2669 /*********************************/ 2670 //If the FIFO is 2 from EMPTY 2671 /*********************************/ 2672 end else if (num_read_words == 2) begin 2673 2674 //no write attempted 2675 ideal_wr_ack <= 0; 2676 2677 //FIFO is not near FULL 2678 ideal_full <= 1'b0; 2679 ideal_almost_full <= 1'b0; 2680 2681 //Read successful 2682 ideal_valid <= 1'b1; 2683 2684 //FIFO is going ALMOST_EMPTY 2685 ideal_empty <= 1'b0; 2686 ideal_almost_empty <= 1'b1; 2687 2688 //Get the data from the FIFO 2689 read_fifo; 2690 num_bits <= num_bits - C_DOUT_WIDTH; 2691 2692 2693 2694 /*********************************/ 2695 //If the FIFO is one from full 2696 /*********************************/ 2697 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 2698 2699 //no write attempted 2700 ideal_wr_ack <= 0; 2701 2702 //FIFO is leaving ALMOST FULL 2703 ideal_full <= 1'b0; 2704 ideal_almost_full <= 1'b0; 2705 2706 //Read successful 2707 ideal_valid <= 1'b1; 2708 2709 //Not near empty 2710 ideal_empty <= 1'b0; 2711 ideal_almost_empty <= 1'b0; 2712 2713 //Read from the FIFO 2714 read_fifo; 2715 num_bits <= num_bits - C_DOUT_WIDTH; 2716 2717 2718 /*********************************/ 2719 // FIFO is FULL 2720 /*********************************/ 2721 end else if (num_write_words >= C_FIFO_WR_DEPTH) 2722 begin 2723 //no write attempted 2724 ideal_wr_ack <= 0; 2725 2726 //FIFO is leaving FULL, but is still ALMOST_FULL 2727 ideal_full <= 1'b0; 2728 ideal_almost_full <= 1'b1; 2729 2730 //Read successful 2731 ideal_valid <= 1'b1; 2732 2733 //Not near empty 2734 ideal_empty <= 1'b0; 2735 ideal_almost_empty <= 1'b0; 2736 2737 //Read from the FIFO 2738 read_fifo; 2739 num_bits <= num_bits - C_DOUT_WIDTH; 2740 2741 /*********************************/ 2742 //If the FIFO is not near EMPTY or FULL 2743 /*********************************/ 2744 end else begin 2745 //no write attemped 2746 ideal_wr_ack <= 0; 2747 2748 //Not near empty 2749 ideal_full <= 1'b0; 2750 ideal_almost_full <= 1'b0; 2751 2752 //Read successful 2753 ideal_valid <= 1'b1; 2754 2755 //Not near empty 2756 ideal_empty <= 1'b0; 2757 ideal_almost_empty <= 1'b0; 2758 2759 //Read from the FIFO 2760 read_fifo; 2761 num_bits <= num_bits - C_DOUT_WIDTH; 2762 2763 2764 end // average read 2765 2766 2767 /**********************************************************************/ 2768 // Synchronous FIFO Condition #3 : Reading and writing 2769 /**********************************************************************/ 2770 end else if (WR_EN & RD_EN) begin 2771 2772 /*********************************/ 2773 // FIFO is FULL 2774 /*********************************/ 2775 if (num_write_words >= C_FIFO_WR_DEPTH) begin 2776 2777 ideal_wr_ack <= 0; 2778 2779 //Read will be successful, so FIFO will leave FULL 2780 ideal_full <= 1'b0; 2781 ideal_almost_full <= 1'b1; 2782 2783 //Read successful 2784 ideal_valid <= 1'b1; 2785 2786 //Not near empty 2787 ideal_empty <= 1'b0; 2788 ideal_almost_empty <= 1'b0; 2789 2790 //Read from the FIFO 2791 read_fifo; 2792 num_bits <= num_bits - C_DOUT_WIDTH; 2793 2794 2795 /*********************************/ 2796 // FIFO is reporting FULL, but it is empty 2797 // (This is a special case, when coming out of RST 2798 /*********************************/ 2799 end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin 2800 2801 ideal_wr_ack <= 0; 2802 2803 //Read will be successful, so FIFO will leave FULL 2804 ideal_full <= 1'b0; 2805 ideal_almost_full <= 1'b0; 2806 2807 //Read unsuccessful 2808 ideal_valid <= 1'b0; 2809 2810 //Report empty condition 2811 ideal_empty <= 1'b1; 2812 ideal_almost_empty <= 1'b1; 2813 2814 //Do not read from empty FIFO 2815 // Read from the FIFO 2816 2817 2818 /*********************************/ 2819 //If the FIFO is one from full 2820 /*********************************/ 2821 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 2822 2823 //Write successful 2824 ideal_wr_ack <= 1; 2825 2826 //FIFO will remain ALMOST_FULL 2827 ideal_full <= 1'b0; 2828 ideal_almost_full <= 1'b1; 2829 2830 // put the data into the FIFO 2831 write_fifo; 2832 2833 //Read successful 2834 ideal_valid <= 1'b1; 2835 2836 //Not near empty 2837 ideal_empty <= 1'b0; 2838 ideal_almost_empty <= 1'b0; 2839 2840 //Read from the FIFO 2841 read_fifo; 2842 num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 2843 2844 /*********************************/ 2845 //If the FIFO is ALMOST EMPTY 2846 /*********************************/ 2847 end else if (num_read_words == 1) begin 2848 2849 //Write successful 2850 ideal_wr_ack <= 1; 2851 2852 // Not near FULL 2853 ideal_full <= 1'b0; 2854 ideal_almost_full <= 1'b0; 2855 2856 // put the data into the FIFO 2857 write_fifo; 2858 2859 //Read successful 2860 ideal_valid <= 1'b1; 2861 2862 //FIFO will stay ALMOST_EMPTY 2863 ideal_empty <= 1'b0; 2864 ideal_almost_empty <= 1'b1; 2865 2866 //Read from the FIFO 2867 read_fifo; 2868 num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 2869 2870 2871 /*********************************/ 2872 //If the FIFO is EMPTY 2873 /*********************************/ 2874 end else if (num_read_words == 0) begin 2875 2876 //Write successful 2877 ideal_wr_ack <= 1; 2878 2879 // Not near FULL 2880 ideal_full <= 1'b0; 2881 ideal_almost_full <= 1'b0; 2882 2883 // put the data into the FIFO 2884 write_fifo; 2885 2886 //Read will fail 2887 ideal_valid <= 1'b0; 2888 2889 //FIFO will leave EMPTY 2890 ideal_empty <= 1'b0; 2891 ideal_almost_empty <= 1'b1; 2892 2893 // No read 2894 num_bits <= num_bits + C_DIN_WIDTH; 2895 2896 2897 /*********************************/ 2898 //If the FIFO is not near EMPTY or FULL 2899 /*********************************/ 2900 end else begin 2901 2902 //Write successful 2903 ideal_wr_ack <= 1; 2904 2905 // Not near FULL 2906 ideal_full <= 1'b0; 2907 ideal_almost_full <= 1'b0; 2908 2909 // put the data into the FIFO 2910 write_fifo; 2911 2912 //Read successful 2913 ideal_valid <= 1'b1; 2914 2915 // Not near EMPTY 2916 ideal_empty <= 1'b0; 2917 ideal_almost_empty <= 1'b0; 2918 2919 //Read from the FIFO 2920 read_fifo; 2921 num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 2922 2923 end // average case 2924 2925 /**********************************************************************/ 2926 // Synchronous FIFO Condition #4 : Not reading or writing 2927 /*** 2928 *******************************************************************/ 2929 end else begin 2930 2931 /*********************************/ 2932 // FIFO is FULL 2933 /*********************************/ 2934 if (num_write_words >= C_FIFO_WR_DEPTH) begin 2935 2936 //No write 2937 ideal_wr_ack <= 0; 2938 ideal_full <= 1'b1; 2939 ideal_almost_full <= 1'b1; 2940 2941 //No read 2942 ideal_valid <= 1'b0; 2943 ideal_empty <= 1'b0; 2944 ideal_almost_empty <= 1'b0; 2945 2946 //No change to memory 2947 2948 /*********************************/ 2949 //If the FIFO is one from full 2950 /*********************************/ 2951 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 2952 2953 //No write 2954 ideal_wr_ack <= 0; 2955 ideal_full <= 1'b0; 2956 ideal_almost_full <= 1'b1; 2957 2958 //No read 2959 ideal_valid <= 1'b0; 2960 ideal_empty <= 1'b0; 2961 ideal_almost_empty <= 1'b0; 2962 2963 //No change to memory 2964 2965 /*********************************/ 2966 //If the FIFO is ALMOST EMPTY 2967 /*********************************/ 2968 end else if (num_read_words == 1) begin 2969 //No write 2970 ideal_wr_ack <= 0; 2971 ideal_full <= 1'b0; 2972 ideal_almost_full <= 1'b0; 2973 2974 //No read 2975 ideal_valid <= 1'b0; 2976 ideal_empty <= 1'b0; 2977 ideal_almost_empty <= 1'b1; 2978 2979 //No change to memory 2980 2981 end // almost empty 2982 2983 2984 /*********************************/ 2985 //If the FIFO is EMPTY 2986 /*********************************/ 2987 else if (num_read_words == 0) 2988 begin 2989 //No write 2990 ideal_wr_ack <= 0; 2991 ideal_full <= 1'b0; 2992 ideal_almost_full <= 1'b0; 2993 2994 //No read 2995 ideal_valid <= 1'b0; 2996 ideal_empty <= 1'b1; 2997 ideal_almost_empty <= 1'b1; 2998 2999 //No change to memory 3000 3001 /*********************************/ 3002 //If the FIFO is not near EMPTY or FULL 3003 /*********************************/ 3004 end else begin 3005 3006 //No write 3007 ideal_wr_ack <= 0; 3008 ideal_full <= 1'b0; 3009 ideal_almost_full <= 1'b0; 3010 3011 //No read 3012 ideal_valid <= 1'b0; 3013 ideal_empty <= 1'b0; 3014 ideal_almost_empty <= 1'b0; 3015 3016 //No change to memory 3017 3018 end // average case 3019 3020 end // neither reading or writing 3021 3022 num_read_words_q <= num_read_words; 3023 num_write_words_q <= num_write_words; 3024 3025 end //normal operating conditions 3026 end 3027 3028 end // block: gen_fifo 3029 3030 //Generate overflow and underflow flags seperately 3031 //because they don't support async rst 3032 always @(posedge CLK) begin 3033 ideal_overflow <= WR_EN & ideal_full; 3034 ideal_underflow <= ideal_empty & RD_EN; 3035 end 3036 3037 always @(posedge CLK or posedge rst_i) begin : gen_fifo_p 3038 3039 /****** Reset fifo - Async Reset****************************************/ 3040 //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core. 3041 //if (rst_i || rst_q) begin //was in v3.1 3042 if (rst_i) begin //v3.2 3043 ideal_prog_full <= C_FULL_FLAGS_RST_VAL; 3044 ideal_prog_empty <= 1'b1; 3045 prog_full_d <= C_FULL_FLAGS_RST_VAL; 3046 prog_empty_d <= 1'b1; 3047 3048 end else begin 3049 if (srst_i) begin 3050 //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. 3051 if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin 3052 ideal_prog_full <= 1'b0; 3053 ideal_prog_empty <= 1'b1; 3054 prog_full_d <= 1'b0; 3055 prog_empty_d <= 1'b1; 3056 end 3057 end else begin 3058 3059 /***************************************************************** 3060 * Programmable FULL flags 3061 ****************************************************************/ 3062 //Single constant threshold 3063 if (C_PROG_FULL_TYPE == 1) begin 3064 if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) 3065 && WR_EN && !RD_EN) begin 3066 prog_full_d <= 1'b1; 3067 end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) 3068 && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 3069 prog_full_d <= 1'b0; 3070 end 3071 3072 //Dual constant thresholds 3073 end else if (C_PROG_FULL_TYPE == 2) begin 3074 if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) 3075 && WR_EN && !RD_EN) begin 3076 prog_full_d <= 1'b1; 3077 end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) 3078 && RD_EN && !WR_EN) begin 3079 prog_full_d <= 1'b0; 3080 end 3081 3082 //Single input threshold 3083 end else if (C_PROG_FULL_TYPE == 3) begin 3084 if ((num_write_words == PROG_FULL_THRESH-1) 3085 && WR_EN && !RD_EN) begin 3086 prog_full_d <= 1'b1; 3087 end else if ((num_write_words == PROG_FULL_THRESH) 3088 && !WR_EN && RD_EN) begin 3089 prog_full_d <= 1'b0; 3090 end else if (num_write_words >= PROG_FULL_THRESH) begin 3091 prog_full_d <= 1'b1; 3092 end else if (num_write_words < PROG_FULL_THRESH) begin 3093 prog_full_d <= 1'b0; 3094 end 3095 3096 //Dual input thresholds 3097 end else begin 3098 if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) 3099 && WR_EN && !RD_EN) begin 3100 prog_full_d <= 1'b1; 3101 end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) 3102 && !WR_EN && RD_EN)begin 3103 prog_full_d <= 1'b0; 3104 end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin 3105 prog_full_d <= 1'b1; 3106 end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin 3107 prog_full_d <= 1'b0; 3108 end 3109 end 3110 3111 /***************************************************************** 3112 * Programmable EMPTY flags 3113 ****************************************************************/ 3114 //Single constant threshold 3115 if (C_PROG_EMPTY_TYPE == 1) begin 3116 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 3117 && RD_EN && !WR_EN) begin 3118 prog_empty_d <= 1'b1; 3119 end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) 3120 && WR_EN && !RD_EN) begin 3121 prog_empty_d <= 1'b0; 3122 end 3123 //Dual constant thresholds 3124 end else if (C_PROG_EMPTY_TYPE == 2) begin 3125 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 3126 && RD_EN && !WR_EN) begin 3127 prog_empty_d <= 1'b1; 3128 end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) 3129 && !RD_EN && WR_EN) begin 3130 prog_empty_d <= 1'b0; 3131 end 3132 3133 //Single input threshold 3134 end else if (C_PROG_EMPTY_TYPE == 3) begin 3135 if ((num_read_words == PROG_EMPTY_THRESH+1) 3136 && RD_EN && !WR_EN) begin 3137 prog_empty_d <= 1'b1; 3138 end else if ((num_read_words == PROG_EMPTY_THRESH) 3139 && !RD_EN && WR_EN) begin 3140 prog_empty_d <= 1'b0; 3141 end else if (num_read_words <= PROG_EMPTY_THRESH) begin 3142 prog_empty_d <= 1'b1; 3143 end else if (num_read_words > PROG_EMPTY_THRESH)begin 3144 prog_empty_d <= 1'b0; 3145 end 3146 3147 //Dual input thresholds 3148 end else begin 3149 if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin 3150 prog_empty_d <= 1'b1; 3151 end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) 3152 && RD_EN && !WR_EN) begin 3153 prog_empty_d <= 1'b1; 3154 end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin 3155 prog_empty_d <= 1'b0; 3156 end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) 3157 && !RD_EN && WR_EN) begin 3158 prog_empty_d <= 1'b0; 3159 end 3160 end 3161 3162 ideal_prog_empty <= prog_empty_d; 3163 if (rst_q && !rst_i) begin 3164 ideal_prog_full <= 1'b0; 3165 end else begin 3166 ideal_prog_full <= prog_full_d; 3167 end 3168 3169 end //if (srst_i) begin 3170 end //if (rst_i) begin 3171 end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p 3172endmodule // fifo_generator_v4_3_bhv_ver_ss 3173 3174 3175module fifo_generator_v4_3_bhv_ver_preload0 3176 ( 3177 RD_CLK, 3178 RD_RST, 3179 RD_EN, 3180 FIFOEMPTY, 3181 FIFODATA, 3182 USERDATA, 3183 USERVALID, 3184 USERUNDERFLOW, 3185 USEREMPTY, 3186 USERALMOSTEMPTY, 3187 RAMVALID, 3188 FIFORDEN 3189 ); 3190 3191 3192 parameter C_DOUT_RST_VAL = ""; 3193 parameter C_DOUT_WIDTH = 8; 3194 parameter C_HAS_RST = 0; 3195 parameter C_USERVALID_LOW = 0; 3196 parameter C_USERUNDERFLOW_LOW = 0; 3197 3198 3199 input RD_CLK; 3200 input RD_RST; 3201 input RD_EN; 3202 input FIFOEMPTY; 3203 input [C_DOUT_WIDTH-1:0] FIFODATA; 3204 output [C_DOUT_WIDTH-1:0] USERDATA; 3205 output USERVALID; 3206 output USERUNDERFLOW; 3207 output USEREMPTY; 3208 output USERALMOSTEMPTY; 3209 output RAMVALID; 3210 output FIFORDEN; 3211 3212 wire RD_CLK; 3213 wire RD_RST; 3214 wire RD_EN; 3215 wire FIFOEMPTY; 3216 wire [C_DOUT_WIDTH-1:0] FIFODATA; 3217 reg [C_DOUT_WIDTH-1:0] USERDATA; 3218 wire USERVALID; 3219 wire USERUNDERFLOW; 3220 wire USEREMPTY; 3221 wire USERALMOSTEMPTY; 3222 wire RAMVALID; 3223 wire FIFORDEN; 3224 3225 wire preloadstage1; 3226 wire preloadstage2; 3227 reg ram_valid_i; 3228 reg read_data_valid_i; 3229 wire ram_regout_en; 3230 wire ram_rd_en; 3231 reg empty_i = 1'b1; 3232 reg empty_q = 1'b1; 3233 reg rd_en_q = 1'b0; //Fix for CR:236270 in v3.2 //prasanna 3234 reg almost_empty_i = 1'b1; 3235 reg almost_empty_q = 1'b1; 3236 wire rd_rst_i; 3237 3238 3239/************************************************************************* 3240* FUNCTIONS 3241*************************************************************************/ 3242 3243 /************************************************************************* 3244 * hexstr_conv 3245 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 3246 ***********************************************************************/ 3247 function [C_DOUT_WIDTH-1:0] hexstr_conv; 3248 input [(C_DOUT_WIDTH*8)-1:0] def_data; 3249 3250 integer index,i,j; 3251 reg [3:0] bin; 3252 3253 begin 3254 index = 0; 3255 hexstr_conv = 'b0; 3256 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 3257 begin 3258 case (def_data[7:0]) 3259 8'b00000000 : 3260 begin 3261 bin = 4'b0000; 3262 i = -1; 3263 end 3264 8'b00110000 : bin = 4'b0000; 3265 8'b00110001 : bin = 4'b0001; 3266 8'b00110010 : bin = 4'b0010; 3267 8'b00110011 : bin = 4'b0011; 3268 8'b00110100 : bin = 4'b0100; 3269 8'b00110101 : bin = 4'b0101; 3270 8'b00110110 : bin = 4'b0110; 3271 8'b00110111 : bin = 4'b0111; 3272 8'b00111000 : bin = 4'b1000; 3273 8'b00111001 : bin = 4'b1001; 3274 8'b01000001 : bin = 4'b1010; 3275 8'b01000010 : bin = 4'b1011; 3276 8'b01000011 : bin = 4'b1100; 3277 8'b01000100 : bin = 4'b1101; 3278 8'b01000101 : bin = 4'b1110; 3279 8'b01000110 : bin = 4'b1111; 3280 8'b01100001 : bin = 4'b1010; 3281 8'b01100010 : bin = 4'b1011; 3282 8'b01100011 : bin = 4'b1100; 3283 8'b01100100 : bin = 4'b1101; 3284 8'b01100101 : bin = 4'b1110; 3285 8'b01100110 : bin = 4'b1111; 3286 default : 3287 begin 3288 bin = 4'bx; 3289 end 3290 endcase 3291 for( j=0; j<4; j=j+1) 3292 begin 3293 if ((index*4)+j < C_DOUT_WIDTH) 3294 begin 3295 hexstr_conv[(index*4)+j] = bin[j]; 3296 end 3297 end 3298 index = index + 1; 3299 def_data = def_data >> 8; 3300 end 3301 end 3302 endfunction 3303 3304initial 3305 begin 3306 ram_valid_i = 1'b0; 3307 read_data_valid_i = 1'b0; 3308 USERDATA = hexstr_conv(C_DOUT_RST_VAL); 3309 end 3310 3311 3312 //****************************************************************************** 3313 // connect up optional reset 3314 //****************************************************************************** 3315 assign rd_rst_i = C_HAS_RST ? RD_RST : 0; 3316 3317 3318 //****************************************************************************** 3319 // preloadstage2 indicates that stage2 needs to be updated. This is true 3320 // whenever read_data_valid is false, and RAM_valid is true. 3321 //****************************************************************************** 3322 assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); 3323 3324 //****************************************************************************** 3325 // preloadstage1 indicates that stage1 needs to be updated. This is true 3326 // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is 3327 // false (indicating that Stage1 needs updating), or preloadstage2 is active 3328 // (indicating that Stage2 is going to update, so Stage1, therefore, must 3329 // also be updated to keep it valid. 3330 //****************************************************************************** 3331 assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); 3332 3333 //****************************************************************************** 3334 // Calculate RAM_REGOUT_EN 3335 // The output registers are controlled by the ram_regout_en signal. 3336 // These registers should be updated either when the output in Stage2 is 3337 // invalid (preloadstage2), OR when the user is reading, in which case the 3338 // Stage2 value will go invalid unless it is replenished. 3339 //****************************************************************************** 3340 assign ram_regout_en = preloadstage2; 3341 3342 //****************************************************************************** 3343 // Calculate RAM_RD_EN 3344 // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to 3345 // update the value in Stage1. 3346 // One case when this happens is when preloadstage1=true, which indicates 3347 // that the data in Stage1 or Stage2 is invalid, and needs to automatically 3348 // be updated. 3349 // The other case is when the user is reading from the FIFO, which guarantees 3350 // that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is 3351 // replinished by data from the memory. So, as long as the RAM has data in it, 3352 // a read of the RAM should occur. 3353 //****************************************************************************** 3354 assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; 3355 3356 //****************************************************************************** 3357 // Calculate RAMVALID_P0_OUT 3358 // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. 3359 // 3360 // If the RAM is being read from on this clock cycle (ram_rd_en=1), then 3361 // RAMVALID_P0_OUT is certainly going to be true. 3362 // If the RAM is not being read from, but the output registers are being 3363 // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, 3364 // therefore causing RAMVALID_P0_OUT to be false. 3365 // Otherwise, RAMVALID_P0_OUT will remain unchanged. 3366 //****************************************************************************** 3367 always @ (posedge RD_CLK or posedge rd_rst_i) 3368 begin // PROCESS regout_valid 3369 if (rd_rst_i) // asynchronous reset (active high) 3370 ram_valid_i <= 1'b0; 3371 else 3372 begin 3373 if (ram_rd_en == 1'b1) 3374 ram_valid_i <= 1'b1; 3375 else 3376 if (ram_regout_en == 1'b1) 3377 ram_valid_i <= 1'b0; 3378 else 3379 ram_valid_i <= ram_valid_i; 3380 end //rd_rst_i 3381 end //always 3382 3383 //****************************************************************************** 3384 // Calculate READ_DATA_VALID 3385 // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. 3386 // Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, 3387 // such that the data in Stage1 is propogated into Stage2. 3388 //****************************************************************************** 3389 always @ (posedge RD_CLK or posedge rd_rst_i) 3390 begin 3391 if (rd_rst_i) 3392 read_data_valid_i <= 1'b0; 3393 else 3394 read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); 3395 end //always 3396 3397 3398 //***************************************************************************** 3399 // Calculate EMPTY 3400 // Defined as the inverse of READ_DATA_VALID 3401 // 3402 // Description: 3403 // 3404 // If read_data_valid_i indicates that the output is not valid, 3405 // and there is no valid data on the output of the ram to preload it 3406 // with, then we will report empty. 3407 // 3408 // If there is no valid data on the output of the ram and we are 3409 // reading, then the FIFO will go empty. 3410 // 3411 //***************************************************************************** 3412 always @ (posedge RD_CLK or posedge rd_rst_i) 3413 begin 3414 if (rd_rst_i) // asynchronous reset (active high) 3415 begin 3416 empty_i <= 1'b1; 3417 empty_q <= 1'b1; 3418 end 3419 else // rising clock edge 3420 begin 3421 empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); 3422 empty_q <= empty_i; 3423 end 3424 end //always 3425 3426 //Fix for CR:236270 //prasanna 3427 //Register RD_EN from user to calculate USERUNDERFLOW. 3428 always @ (posedge RD_CLK or posedge rd_rst_i) 3429 begin 3430 if (rd_rst_i) // asynchronous reset (active high) 3431 begin 3432 rd_en_q <= 1'b0; 3433 end 3434 else // rising clock edge 3435 begin 3436 rd_en_q <= RD_EN; 3437 end 3438 end //always 3439 3440 3441 //***************************************************************************** 3442 // Calculate user_almost_empty 3443 // user_almost_empty is defined such that, unless more words are written 3444 // to the FIFO, the next read will cause the FIFO to go EMPTY. 3445 // 3446 // In most cases, whenever the output registers are updated (due to a user 3447 // read or a preload condition), then user_almost_empty will update to 3448 // whatever RAM_EMPTY is. 3449 // 3450 // The exception is when the output is valid, the user is not reading, and 3451 // Stage1 is not empty. In this condition, Stage1 will be preloaded from the 3452 // memory, so we need to make sure user_almost_empty deasserts properly under 3453 // this condition. 3454 //***************************************************************************** 3455 always @ (posedge RD_CLK or posedge rd_rst_i) 3456 begin 3457 if (rd_rst_i) // asynchronous reset (active high) 3458 begin 3459 almost_empty_i <= 1'b1; 3460 almost_empty_q <= 1'b1; 3461 end 3462 else // rising clock edge 3463 begin 3464 if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) 3465 begin 3466 almost_empty_i <= FIFOEMPTY; 3467 end 3468 almost_empty_q <= empty_i; 3469 end 3470 end //always 3471 3472 3473 assign USEREMPTY = empty_i; 3474 assign USERALMOSTEMPTY = almost_empty_i; 3475 assign FIFORDEN = ram_rd_en; 3476 assign RAMVALID = ram_valid_i; 3477 assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; 3478 //assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) 3479 assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna 3480 3481 always @ (posedge RD_CLK or posedge rd_rst_i) 3482 begin 3483 if (rd_rst_i) // asynchronous reset (active high) 3484 USERDATA <= hexstr_conv(C_DOUT_RST_VAL); 3485 else // rising clock edge 3486 if (ram_regout_en) 3487 USERDATA <= FIFODATA; 3488 end //always 3489 3490 3491 3492 3493 3494endmodule 3495