/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/lang/clover/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 37 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 40 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/ |
H A D | brw_vec4_reg_allocate.cpp | 33 assign(unsigned int *reg_hw_locations, backend_reg *reg) in assign() argument 36 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign()
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H A D | brw_fs_reg_allocate.cpp | 36 assign_reg(unsigned *reg_hw_locations, fs_reg *reg) in assign_reg() argument 39 reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; in assign_reg()
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