| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/ |
| H A D | demo_one_gig_pcs_pma_mdio.v | 221 reg reg_wr_req; register
278 .reg_wr_req (reg_wr_req),
414 reg_wr_req <= 1'b1;
416 reg_wr_req <= 1'b0;
423 reg_wr_req <= 1'b1;
425 reg_wr_req <= 1'b0;
432 reg_wr_req <= 1'b1;
434 reg_wr_req <= 1'b0;
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| H A D | one_gig_eth_loopback_tb.sv | 100 .reg_wr_req (/*reg_wr_req*/),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | ctrlport_to_regport.v | 41 output reg reg_wr_req = 1'b0, port
54 reg_wr_req <= 1'b0;
62 reg_wr_req <= 1'b0;
67 reg_wr_req <= 1'b1;
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| H A D | axi_crossbar_regport.v | 26 input reg_wr_req, port
94 if (reg_wr_req)
142 .reg_wr_req(reg_wr_req),
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| H A D | regport_to_xbar_settingsbus.v | 34 input reg_wr_req, port
95 .reg_wr_req(reg_wr_req),
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| H A D | regport_to_settingsbus.v | 28 input reg_wr_req, port
43 assign set_stb_int = reg_wr_req && (reg_wr_addr >= BASE) && (reg_wr_addr <= END_ADDR);
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| H A D | axil_regport_master.v | 77 output reg_wr_req, port
159 .o_tvalid(reg_wr_req), .o_tready(1'b1)
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| H A D | mdio_master.v | 22 input reg_wr_req, port
181 if (reg_wr_req) begin
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | n3xx_sfp_wrapper.v | 167 wire reg_wr_req; net
209 .reg_wr_req (reg_wr_req),
264 .reg_wr_req (reg_wr_req),
441 .reg_wr_req (reg_wr_req),
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| H A D | n3xx_mgt_io_core.v | 53 input reg_wr_req, port
160 end else if (reg_wr_req) begin
248 .reg_wr_req (reg_wr_req),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/ |
| H A D | eth_internal.v | 90 wire reg_wr_req; net
134 .reg_wr_req (reg_wr_req),
286 .reg_wr_req (reg_wr_req),
373 end else if (reg_wr_req) begin
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| H A D | eth_interface.v | 21 input reg_wr_req, port
125 if (reg_wr_req)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n3xx_mgt_channel_wrapper.v | 192 wire reg_wr_req; net
234 .reg_wr_req (reg_wr_req),
286 .reg_wr_req (reg_wr_req),
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| H A D | n3xx_mgt_wrapper.v | 38 input wire reg_wr_req, port
210 .reg_wr_req (reg_wr_req),
412 .reg_wr_req (reg_wr_req),
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| H A D | n3xx_mgt_io_core.v | 56 input reg_wr_req, port
173 end else if (reg_wr_req) begin
261 .reg_wr_req (reg_wr_req),
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| H A D | n3xx_core.v | 448 .reg_wr_req (reg_wr_req_npio),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/ |
| H A D | eth_ipv4_interface.sv | 50 input logic reg_wr_req, port
123 if (reg_wr_req)
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/ |
| H A D | eth_ifc_synth_test.sv | 38 input logic reg_wr_req, port
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| H A D | eth_ifc_tb.sv | 101 reg reg_wr_req = 1'b0; register
225 reg_wr_req = 1'b1;
229 reg_wr_req = 1'b0;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/aurora_loopback/ |
| H A D | aurora_loopback_tb.sv | 225 .reg_wr_req(reg_wr_req_s), //input reg_wr_req,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/ |
| H A D | n3xx.v | 1392 .reg_wr_req (reg_wr_req_npio),
1449 .reg_wr_req (reg_wr_req_npio),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/ |
| H A D | n3xx.v | 1382 .reg_wr_req (reg_wr_req_npio),
1439 .reg_wr_req (reg_wr_req_npio),
|