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Searched refs:s_ctrlport_req_rd (Results 1 – 25 of 64) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/
H A Dradio_core.v36 input wire s_ctrlport_req_rd, port
140 .s_ctrlport_req_rd (s_ctrlport_req_rd),
206 .s_ctrlport_req_rd (2'b0),
304 .s_ctrlport_req_rd (ctrlport_tx_req_rd),
343 .s_ctrlport_req_rd (ctrlport_rx_req_rd),
H A Drfnoc_block_radio.v211 .s_ctrlport_req_rd (1'b0),
286 .s_ctrlport_req_rd (ctrlport_reg_req_rd),
348 .s_ctrlport_req_rd (ctrlport_core_req_rd),
396 .s_ctrlport_req_rd ({NUM_PORTS{1'b0}}),
480 .s_ctrlport_req_rd (ctrlport_radios_req_rd[i]),
H A Dnoc_shell_radio.v91 input wire s_ctrlport_req_rd, port
219 .s_ctrlport_req_rd (s_ctrlport_req_rd),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/
H A Dctrlport_reg_ro.v61 input wire s_ctrlport_req_rd, port
141 … if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
167 … if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
H A Dctrlport_splitter.v40 input wire s_ctrlport_req_rd, port
67 assign m_ctrlport_req_rd = s_ctrlport_req_rd;
89 assign m_ctrlport_req_rd[i] = s_ctrlport_req_rd;
H A Dctrlport_timer.v44 input wire s_ctrlport_req_rd, port
86 .i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data,
88 .i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
H A Dctrlport_clk_cross.v23 input wire s_ctrlport_req_rd, port
90 s_ctrlport_req_rd,
112 .valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
H A Dctrlport_terminator.v20 input wire s_ctrlport_req_rd, port
39 s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
H A Dtimekeeper.v29 input wire s_ctrlport_req_rd, port
73 .s_ctrlport_req_rd (s_ctrlport_req_rd),
H A Dctrlport_gate.v23 input wire s_ctrlport_req_rd, port
62 m_ctrlport_req_rd <= s_ctrlport_req_rd;
H A Dctrlport_combiner.v41 input wire [ NUM_MASTERS-1:0] s_ctrlport_req_rd, port
118 if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
122 req_rd[i] <= s_ctrlport_req_rd[i];
H A Dctrlport_decoder_param.v63 input wire s_ctrlport_req_rd, port
121 m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
H A Dctrlport_decoder.v47 input wire s_ctrlport_req_rd, port
103 m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
H A Dctrlport_reg_rw.v69 input wire s_ctrlport_req_rd, port
231 if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
H A Dctrlport_to_settings_bus.v67 input wire s_ctrlport_req_rd, port
143 if (s_ctrlport_req_rd && port_num < NUM_PORTS) begin
H A Dnoc_shell_generic_ctrlport_pyld_chdr.v73 input wire s_ctrlport_req_rd, port
180 .s_ctrlport_req_rd (s_ctrlport_req_rd ),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/
H A Dctrlport_to_regport.v35 input wire s_ctrlport_req_rd, port
76 if (s_ctrlport_req_rd) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/
H A Daxi_ram_fifo_bist.v41 input wire s_ctrlport_req_rd, port
152 .s_ctrlport_req_rd (s_ctrlport_req_rd),
H A Daxi_ram_fifo_bist_regs.v37 input wire s_ctrlport_req_rd, port
115 if (s_ctrlport_req_rd) begin
H A Daxi_ram_fifo_regs.v35 input wire s_ctrlport_req_rd, port
134 if (s_ctrlport_req_rd) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/rfnoc_blocktool/templates/modules/
H A Dctrlport_connect_template.mako24 .s_ctrlport_req_rd (s_ctrlport_req_rd),
H A Dctrlport_modules_template.mako34 ….s_ctrlport_req_rd (${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/
H A Drfnoc_window_core.v31 input wire s_ctrlport_req_rd, port
101 if (s_ctrlport_req_rd) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/
H A Drfnoc_fir_filter_core.v75 input wire s_ctrlport_req_rd, port
148 if (s_ctrlport_req_rd) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/
H A Drfnoc_block_siggen.v190 .s_ctrlport_req_rd (m_ctrlport_req_rd),
224 .s_ctrlport_req_rd (ctrlport_req_rd [port* 1 +: 1]),

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