/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/ |
H A D | radio_core.v | 36 input wire s_ctrlport_req_rd, port 140 .s_ctrlport_req_rd (s_ctrlport_req_rd), 206 .s_ctrlport_req_rd (2'b0), 304 .s_ctrlport_req_rd (ctrlport_tx_req_rd), 343 .s_ctrlport_req_rd (ctrlport_rx_req_rd),
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H A D | rfnoc_block_radio.v | 211 .s_ctrlport_req_rd (1'b0), 286 .s_ctrlport_req_rd (ctrlport_reg_req_rd), 348 .s_ctrlport_req_rd (ctrlport_core_req_rd), 396 .s_ctrlport_req_rd ({NUM_PORTS{1'b0}}), 480 .s_ctrlport_req_rd (ctrlport_radios_req_rd[i]),
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H A D | noc_shell_radio.v | 91 input wire s_ctrlport_req_rd, port 219 .s_ctrlport_req_rd (s_ctrlport_req_rd),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/ |
H A D | ctrlport_reg_ro.v | 61 input wire s_ctrlport_req_rd, port 141 … if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin 167 … if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
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H A D | ctrlport_splitter.v | 40 input wire s_ctrlport_req_rd, port 67 assign m_ctrlport_req_rd = s_ctrlport_req_rd; 89 assign m_ctrlport_req_rd[i] = s_ctrlport_req_rd;
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H A D | ctrlport_timer.v | 44 input wire s_ctrlport_req_rd, port 86 .i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data, 88 .i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
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H A D | ctrlport_clk_cross.v | 23 input wire s_ctrlport_req_rd, port 90 s_ctrlport_req_rd, 112 .valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
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H A D | ctrlport_terminator.v | 20 input wire s_ctrlport_req_rd, port 39 s_ctrlport_resp_ack <= s_ctrlport_req_wr | s_ctrlport_req_rd;
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H A D | timekeeper.v | 29 input wire s_ctrlport_req_rd, port 73 .s_ctrlport_req_rd (s_ctrlport_req_rd),
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H A D | ctrlport_gate.v | 23 input wire s_ctrlport_req_rd, port 62 m_ctrlport_req_rd <= s_ctrlport_req_rd;
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H A D | ctrlport_combiner.v | 41 input wire [ NUM_MASTERS-1:0] s_ctrlport_req_rd, port 118 if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin 122 req_rd[i] <= s_ctrlport_req_rd[i];
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H A D | ctrlport_decoder_param.v | 63 input wire s_ctrlport_req_rd, port 121 m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
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H A D | ctrlport_decoder.v | 47 input wire s_ctrlport_req_rd, port 103 m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & decoder[i];
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H A D | ctrlport_reg_rw.v | 69 input wire s_ctrlport_req_rd, port 231 if (s_ctrlport_req_addr[19 : BYTE_ADDR_W] == ADDR[19 : BYTE_ADDR_W] && s_ctrlport_req_rd) begin
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H A D | ctrlport_to_settings_bus.v | 67 input wire s_ctrlport_req_rd, port 143 if (s_ctrlport_req_rd && port_num < NUM_PORTS) begin
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H A D | noc_shell_generic_ctrlport_pyld_chdr.v | 73 input wire s_ctrlport_req_rd, port 180 .s_ctrlport_req_rd (s_ctrlport_req_rd ),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
H A D | ctrlport_to_regport.v | 35 input wire s_ctrlport_req_rd, port 76 if (s_ctrlport_req_rd) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/ |
H A D | axi_ram_fifo_bist.v | 41 input wire s_ctrlport_req_rd, port 152 .s_ctrlport_req_rd (s_ctrlport_req_rd),
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H A D | axi_ram_fifo_bist_regs.v | 37 input wire s_ctrlport_req_rd, port 115 if (s_ctrlport_req_rd) begin
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H A D | axi_ram_fifo_regs.v | 35 input wire s_ctrlport_req_rd, port 134 if (s_ctrlport_req_rd) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/rfnoc_blocktool/templates/modules/ |
H A D | ctrlport_connect_template.mako | 24 .s_ctrlport_req_rd (s_ctrlport_req_rd),
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H A D | ctrlport_modules_template.mako | 34 ….s_ctrlport_req_rd (${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "…
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/ |
H A D | rfnoc_window_core.v | 31 input wire s_ctrlport_req_rd, port 101 if (s_ctrlport_req_rd) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/ |
H A D | rfnoc_fir_filter_core.v | 75 input wire s_ctrlport_req_rd, port 148 if (s_ctrlport_req_rd) begin
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/ |
H A D | rfnoc_block_siggen.v | 190 .s_ctrlport_req_rd (m_ctrlport_req_rd), 224 .s_ctrlport_req_rd (ctrlport_req_rd [port* 1 +: 1]),
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