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/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/risc_cpu/
H A Ddecode.h59 sc_out<bool> next_pc; // next pc ++ ?
62 sc_out<bool> mem_access; // memory access valid
64 sc_out<int> alu_op; // ALU/FPU/MMU Opcode
65 sc_out<bool> mem_write; // memory write enable
67 sc_out<bool> reg_write; // not implemented
68 sc_out<signed int> src_A; // operand A
69 sc_out<signed int> src_B; // operand B
74 sc_out<bool> float_valid; // enable FPU
75 sc_out<bool> mmx_valid; // enable MMU
76 sc_out<bool> pid_valid; // load process ID
[all …]
H A Dfetch.h52 sc_out<bool> ram_cs; // RAM chip select
53 sc_out<bool> ram_we; // RAM write enable for SMC
54 sc_out<unsigned > address; // address send to RAM
55 sc_out<unsigned > smc_instruction; // for self-modifying code
56 sc_out<unsigned> instruction; // instruction send to ID
57 sc_out<bool> instruction_valid; // inst valid
58 sc_out<unsigned > program_counter; // program counter
59 sc_out<bool> interrupt_ack; // interrupt acknowledge
60 sc_out<bool> branch_clear; // clear outstanding branch
61 sc_out<bool> pred_fetch_valid; // branch prediction fetch
[all …]
H A Dpaging.h48 sc_out<unsigned > paging_dout; // output data
49 sc_out<bool> paging_csout; // output cs to cache/BIOS
50 sc_out<bool> paging_weout; // write enable to cache/BIOS
51 sc_out<unsigned > physical_address; // physical address
52 sc_out<unsigned > dataout; // dataout from memory
53 sc_out<bool> data_valid; // data valid
54 sc_out<bool> stall_ifu; // stall IFU if busy
H A Dexec.h51 sc_out<bool> C; // Carry bit
52 sc_out<bool> V; // Overflow bit
53 sc_out<bool> Z; // Zero bit
54 sc_out<signed int> dout; // output data
55 sc_out<bool> out_valid; // output valid
56 sc_out<unsigned> destout; // write to which registers?
H A Ddcache.h46 sc_out<unsigned> destout; // write back to which register
47 sc_out<signed> dataout; // dataram data out
48 sc_out<bool> out_valid; // output valid
49 sc_out<unsigned> stateout; // state output
H A Dfloating.h45 sc_out<signed int> fdout; // FPU output
46 sc_out<bool> fout_valid; // output valid
47 sc_out<unsigned> fdestout; // write to which register
H A Dmmxu.h45 sc_out<signed int> mmxdout; // MMX output
46 sc_out<bool> mmxout_valid; // MMX output valid
47 sc_out<unsigned> mmxdestout; // destination number
H A Dpic.h47 sc_out<bool> intreq; // interrupt request to CPU
48 sc_out<bool> intack; // interrupt acknowledge to devices
49 sc_out<unsigned> vectno; // vector number
H A Dbios.h48 sc_out<unsigned > dataout; // ram data out
49 sc_out<bool> bios_valid; // out valid
50 sc_out<bool> stall_fetch; // stall fetch if output not valid
H A Dicache.h49 sc_out<unsigned > dataout; // ram data out
50 sc_out<bool> icache_valid; // output valid
51 sc_out<bool> stall_fetch; // stall fetch if busy
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/fft/fft_flpt/
H A Dfft.h44 sc_out<float> out_real;
45 sc_out<float> out_imag;
46 sc_out<bool> data_req;
47 sc_out<bool> data_ready;
H A Dsource.h41 sc_out<float> out_real;
42 sc_out<float> out_imag;
43 sc_out<bool> data_valid;
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/fft/fft_fxpt/
H A Dfft.h44 sc_out<sc_int<16> > out_real;
45 sc_out<sc_int<16> > out_imag;
46 sc_out<bool> data_req;
47 sc_out<bool> data_ready;
H A Dsource.h41 sc_out<sc_int<16> > out_real;
42 sc_out<sc_int<16> > out_imag;
43 sc_out<bool> data_valid;
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/pkt_switch/
H A Dswitch.h52 sc_out<pkt> out0;
53 sc_out<pkt> out1;
54 sc_out<pkt> out2;
55 sc_out<pkt> out3;
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/fir/
H A Dstimulus.h40 sc_out<bool> reset; in SC_MODULE()
41 sc_out<bool> input_valid; in SC_MODULE()
42 sc_out<int> sample; in SC_MODULE()
H A Dfir.h43 sc_out<bool> output_data_ready; in SC_MODULE()
44 sc_out<int> result; in SC_MODULE()
H A Dfir_data.h43 sc_out<int> result; in SC_MODULE()
44 sc_out<bool> output_data_ready; in SC_MODULE()
H A Dfir_top.h48 sc_out<bool> OUTPUT_DATA_READY; in SC_MODULE()
49 sc_out<int> RESULT; in SC_MODULE()
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/src/sysc/kernel/
H A Dsc_reset.h47 template<typename DATA> class sc_out; variable
90 sc_reset_finder( bool async, const sc_out<bool>* port_p, bool level,
99 const sc_out<bool>* m_out_p; // Port for which reset is needed.
135 reset_signal_is( bool async, const sc_out<bool>& iface, bool level);
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/pipe/
H A Dnumgen.h42 sc_out<double> out1; //output 1
43 sc_out<double> out2; //output 2
H A Dstage1.h44 sc_out<double> sum; //output 1
45 sc_out<double> diff; //output 2
H A Dstage2.h44 sc_out<double> prod; //output port 1
45 sc_out<double> quot; //output port 2
/dports/misc/vxl/vxl-3.3.2/core/vsl/tests/
H A Dtest_binary_io.cxx23 signed char sc_out = 'k'; in test_binary_io() local
42 vsl_b_write(bfs_out, sc_out); in test_binary_io()
93 TEST("signed char out == signed char in", sc_out, sc_in); in test_binary_io()
94 vsl_print_summary(std::cout, sc_out); in test_binary_io()
226 TEST("Golden signed char out == signed char in", sc_out, sc_in2); in test_binary_io()
/dports/devel/systemc/systemc-2.3.4_pub_rev_20190614/examples/sysc/2.3/include/
H A Dsc_rvd.h165 sc_out<bool> m_ready; // true if this port is ready to read a value.
238 sc_out<D> m_data; // data to be transferred.
240 sc_out<bool> m_valid; // true if m_data has a value to be read.

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