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Searched refs:spill_offset (Results 1 – 25 of 121) sorted by relevance

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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/lang/clover/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp754 assert(spill_offset % 16 == 0); in emit_unspill()
791 unspill_inst->offset = spill_offset; in emit_unspill()
794 unspill_inst->offset = spill_offset; in emit_unspill()
801 spill_offset += reg_size * REG_SIZE; in emit_unspill()
819 assert(spill_offset % 16 == 0); in emit_spill()
851 spill_inst->offset = spill_offset; in emit_spill()
858 spill_offset += reg_size * REG_SIZE; in emit_spill()
1012 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1013 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1080 int subset_spill_offset = spill_offset + in spill_reg()
[all …]
/dports/security/py-pyvex/pyvex-9.0.5405/vex/priv/
H A Dhost_generic_reg_alloc3.c75 UShort spill_offset;
620 vreg_state[v_idx].spill_offset = 0;
931 vreg_state[v_idx].spill_offset
937 vassert((vreg_state[v_idx].spill_offset % 16) == 0);
940 vassert((vreg_state[v_idx].spill_offset % 8) == 0);
949 UShort spill_offset = vreg_state[vs_idx].spill_offset;
954 vreg_state[vd_idx].spill_offset = spill_offset;
970 v_idx, vreg_state[v_idx].spill_offset);
1231 Short spill_offset = 0;
1247 spill_offset = vreg_state[v_idx].spill_offset;
[all …]
/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/VEX/priv/
H A Dhost_generic_reg_alloc3.c75 UShort spill_offset; member
584 vreg_state[v_idx].spill_offset = 0; in doRegisterAllocation_v3()
895 vreg_state[v_idx].spill_offset in doRegisterAllocation_v3()
901 vassert((vreg_state[v_idx].spill_offset % 16) == 0); in doRegisterAllocation_v3()
904 vassert((vreg_state[v_idx].spill_offset % 8) == 0); in doRegisterAllocation_v3()
913 UShort spill_offset = vreg_state[vs_idx].spill_offset; in doRegisterAllocation_v3() local
918 vreg_state[vd_idx].spill_offset = spill_offset; in doRegisterAllocation_v3()
934 v_idx, vreg_state[v_idx].spill_offset); in doRegisterAllocation_v3()
1195 Short spill_offset = 0; in doRegisterAllocation_v3() local
1211 spill_offset = vreg_state[v_idx].spill_offset; in doRegisterAllocation_v3()
[all …]
/dports/devel/valgrind/valgrind-dragonfly-dragonfly/VEX/priv/
H A Dhost_generic_reg_alloc3.c75 UShort spill_offset; member
584 vreg_state[v_idx].spill_offset = 0; in doRegisterAllocation_v3()
895 vreg_state[v_idx].spill_offset in doRegisterAllocation_v3()
901 vassert((vreg_state[v_idx].spill_offset % 16) == 0); in doRegisterAllocation_v3()
904 vassert((vreg_state[v_idx].spill_offset % 8) == 0); in doRegisterAllocation_v3()
913 UShort spill_offset = vreg_state[vs_idx].spill_offset; in doRegisterAllocation_v3() local
918 vreg_state[vd_idx].spill_offset = spill_offset; in doRegisterAllocation_v3()
934 v_idx, vreg_state[v_idx].spill_offset); in doRegisterAllocation_v3()
1195 Short spill_offset = 0; in doRegisterAllocation_v3() local
1211 spill_offset = vreg_state[v_idx].spill_offset; in doRegisterAllocation_v3()
[all …]
/dports/lang/clover/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-libs/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/libosmesa/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/graphics/mesa-dri/mesa-21.3.6/src/broadcom/compiler/
H A Dvir_register_allocate.c218 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
221 c->spill_base, vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
227 struct qinst *position, uint32_t spill_offset) in v3d_emit_tmu_spill() argument
238 tmp = v3d_emit_spill_tmua(c, spill_offset); in v3d_emit_tmu_spill()
253 uint32_t spill_offset = 0; in v3d_spill_reg() local
256 spill_offset = c->spill_size; in v3d_spill_reg()
259 if (spill_offset == 0) in v3d_spill_reg()
292 inst, spill_offset); in v3d_spill_reg()
329 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
347 spill_offset); in v3d_spill_reg()
/dports/www/node10/node-v10.24.1/deps/v8/src/arm64/
H A Dcode-stubs-arm64.cc691 __ Poke(x19, (spill_offset + 0) * kXRegSize); in CallApiFunctionAndReturn()
692 __ Poke(x20, (spill_offset + 1) * kXRegSize); in CallApiFunctionAndReturn()
693 __ Poke(x21, (spill_offset + 2) * kXRegSize); in CallApiFunctionAndReturn()
694 __ Poke(x22, (spill_offset + 3) * kXRegSize); in CallApiFunctionAndReturn()
758 __ Peek(x19, (spill_offset + 0) * kXRegSize); in CallApiFunctionAndReturn()
759 __ Peek(x20, (spill_offset + 1) * kXRegSize); in CallApiFunctionAndReturn()
760 __ Peek(x21, (spill_offset + 2) * kXRegSize); in CallApiFunctionAndReturn()
761 __ Peek(x22, (spill_offset + 3) * kXRegSize); in CallApiFunctionAndReturn()
869 const int spill_offset = 1 + kApiStackSpace; in Generate() local
942 const int spill_offset = 1 + kApiStackSpace; in Generate() local
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp833 uint32_t spill_offset, unsigned count) in emit_unspill() argument
849 spill_offset < (1 << 12) * REG_SIZE); in emit_unspill()
854 unspill_inst->offset = spill_offset; in emit_unspill()
862 spill_offset += reg_size * REG_SIZE; in emit_unspill()
868 uint32_t spill_offset, unsigned count) in emit_spill() argument
878 spill_inst->offset = spill_offset + i * reg_size * REG_SIZE; in emit_spill()
1022 unsigned int spill_offset = fs->last_scratch; in spill_reg() local
1023 assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ in spill_reg()
1069 int subset_spill_offset = spill_offset + in spill_reg()
1097 int subset_spill_offset = spill_offset + in spill_reg()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/broadcom/compiler/
H A Dvir_register_allocate.c200 v3d_emit_spill_tmua(struct v3d_compile *c, uint32_t spill_offset) in v3d_emit_spill_tmua() argument
205 vir_uniform_ui(c, spill_offset)); in v3d_emit_spill_tmua()
213 uint32_t spill_offset = 0; in v3d_spill_reg() local
216 spill_offset = c->spill_size; in v3d_spill_reg()
219 if (spill_offset == 0) in v3d_spill_reg()
250 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()
269 v3d_emit_spill_tmua(c, spill_offset); in v3d_spill_reg()

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