Searched refs:sys_clk_p (Results 1 – 9 of 9) sorted by relevance
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo/ |
H A D | dram_fifo_tb.sv | 21 …`DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clo… 37 .sys_clk_p(sys_clk_p),//use differential clock on N310 74 while (~sys_rst_n) @(posedge sys_clk_p);
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H A D | axis_dram_fifo_single.sv | 14 input sys_clk_p, port 442 .sys_clk_p (sys_clk_p), // From external 100MHz source.
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/ |
H A D | dram_fifo_bist_tb.sv | 21 …`DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generat… 56 .sys_clk_p(sys_clk_p),//use differential clock on N310 97 while (~sys_rst_n) @(posedge sys_clk_p); 101 repeat (200) @(posedge sys_clk_p);
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
H A D | e320_dram.xdc | 7 create_generated_clock -name ddr3_ext_refclk -period 7.5 [get_ports sys_clk_p]
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H A D | e320.v | 84 input wire sys_clk_p, port 664 .sys_clk_p (sys_clk_p),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
H A D | n310_dram.xdc | 8 create_clock -name ddr3_ext_refclk -period 10.0 [get_ports sys_clk_p]
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H A D | mb_pins.xdc | 385 set_property PACKAGE_PIN H9 [get_ports sys_clk_p]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/ |
H A D | n3xx.v | 166 input sys_clk_p, // Differential port 3325 .sys_clk_p (sys_clk_p),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/ |
H A D | n3xx.v | 166 input sys_clk_p, // Differential port 3297 .sys_clk_p (sys_clk_p),
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