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Searched refs:sys_clk_p (Results 1 – 9 of 9) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo/
H A Ddram_fifo_tb.sv21 …`DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generate DDR3 clo…
37 .sys_clk_p(sys_clk_p),//use differential clock on N310
74 while (~sys_rst_n) @(posedge sys_clk_p);
H A Daxis_dram_fifo_single.sv14 input sys_clk_p, port
442 .sys_clk_p (sys_clk_p), // From external 100MHz source.
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/sim/dram_fifo_bist/
H A Ddram_fifo_bist_tb.sv21 …`DEFINE_DIFF_CLK(sys_clk_p, sys_clk_n, 10, 50) //100MHz differential sys_clk to generat…
56 .sys_clk_p(sys_clk_p),//use differential clock on N310
97 while (~sys_rst_n) @(posedge sys_clk_p);
101 repeat (200) @(posedge sys_clk_p);
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A De320_dram.xdc7 create_generated_clock -name ddr3_ext_refclk -period 7.5 [get_ports sys_clk_p]
H A De320.v84 input wire sys_clk_p, port
664 .sys_clk_p (sys_clk_p),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn310_dram.xdc8 create_clock -name ddr3_ext_refclk -period 10.0 [get_ports sys_clk_p]
H A Dmb_pins.xdc385 set_property PACKAGE_PIN H9 [get_ports sys_clk_p]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/
H A Dn3xx.v166 input sys_clk_p, // Differential port
3325 .sys_clk_p (sys_clk_p),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Dn3xx.v166 input sys_clk_p, // Differential port
3297 .sys_clk_p (sys_clk_p),