/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | internals.h | 271 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 767 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 783 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 4074 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 4080 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), 4081 offsetof(CPUARMState, cp15.tcr_el[1])} }, 4093 offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), 4094 offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), 5750 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 6005 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 12777 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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H A D | cpu.c | 212 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | internals.h | 260 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 753 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 769 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 4104 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 4109 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 4110 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 4121 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 4122 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 5611 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5866 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 12429 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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H A D | cpu.c | 211 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | internals.h | 271 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 775 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 791 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3850 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 3856 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), 3857 offsetof(CPUARMState, cp15.tcr_el[1])} }, 3869 offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), 3870 offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), 5526 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5781 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 12515 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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H A D | cpu.c | 212 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | internals.h | 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 958 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 974 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 4059 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 4064 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 4065 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 4076 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 4077 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 5519 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5752 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 12197 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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H A D | cpu.c | 209 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); in arm_cpu_reset()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | internals.h | 231 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 796 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | cpu.h | 312 TCR tcr_el[4]; member
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H A D | helper.c | 2778 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 2782 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 2783 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 3995 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 4228 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 8693 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | internals.h | 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 848 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3543 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 3547 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 3548 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 3558 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 3559 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 4897 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5130 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 8658 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr()
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H A D | cpu.h | 315 TCR tcr_el[4]; member
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | internals.h | 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 848 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 3543 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 3547 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 3548 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 3558 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 3559 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 4897 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5130 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 8658 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr()
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H A D | cpu.h | 315 TCR tcr_el[4]; member
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | internals.h | 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 928 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 4090 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 4095 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 4096 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 4107 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 4108 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 5555 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5788 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 9829 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 11914 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | internals.h | 254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; in extended_addresses_enabled() 928 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { in arm_debug_exception_fsr()
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H A D | helper.c | 4090 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, 4095 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), 4096 offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, 4107 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), 4108 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, 5555 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, 5788 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, 9825 return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; in regime_tcr() 11913 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; in get_phys_addr()
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