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Searched refs:the_clk (Results 1 – 2 of 2) sorted by relevance

/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_clk_concat6.v13 logic the_clk; register
15 assign the_clk = i_clks[3];
17 always @(posedge the_clk) begin
26 if (the_clk)
H A Dt_lib_prot_secret.v46 logic the_clk; register
55 assign the_clk = clk & clk_en_latch;
57 assign the_clk = clk;
61 always @(posedge the_clk) begin