1// DESCRIPTION: Verilator: Verilog Test module 2// This file ONLY is placed into the Public Domain, for any use, 3// without warranty, 2019 by Todd Strader. 4// SPDX-License-Identifier: CC0-1.0 5 6module secret #(parameter GATED_CLK = 0) 7 ( 8 input [31:0] accum_in, 9 output wire [31:0] accum_out, 10 input accum_bypass, 11 output [31:0] accum_bypass_out, 12 input s1_in, 13 output logic s1_out, 14 input s1up_in[2], 15 output logic s1up_out[2], 16 input [1:0] s2_in, 17 output logic [1:0] s2_out, 18 input [7:0] s8_in, 19 output logic [7:0] s8_out, 20 input [32:0] s33_in, 21 output logic [32:0] s33_out, 22 input [63:0] s64_in, 23 output logic [63:0] s64_out, 24 input [64:0] s65_in, 25 output logic [64:0] s65_out, 26 input [128:0] s129_in, 27 output logic [128:0] s129_out, 28 input [3:0] [31:0] s4x32_in, 29 output logic [3:0] [31:0] s4x32_out, 30 /*verilator lint_off LITENDIAN*/ 31 input [0:15] s6x16up_in[0:1][2:0], 32 output logic [0:15] s6x16up_out[0:1][2:0], 33 /*verilator lint_on LITENDIAN*/ 34 input [15:0] s8x16up_in[1:0][0:3], 35 output logic [15:0] s8x16up_out[1:0][0:3], 36 input [15:0] s8x16up_3d_in[1:0][0:1][0:1], 37 output logic [15:0] s8x16up_3d_out[1:0][0:1][0:1], 38 input clk_en, 39 input clk /*verilator clocker*/); 40 41 logic [31:0] secret_accum_q = 0; 42 logic [31:0] secret_value = 7; 43 44 initial $display("created %m"); 45 46 logic the_clk; 47 generate 48 if (GATED_CLK != 0) begin: yes_gated_clock 49 logic clk_en_latch /*verilator clock_enable*/; 50 /* verilator lint_off COMBDLY */ 51 /* verilator lint_off LATCH */ 52 always_comb if (clk == '0) clk_en_latch <= clk_en; 53 /* verilator lint_on LATCH */ 54 /* verilator lint_on COMBDLY */ 55 assign the_clk = clk & clk_en_latch; 56 end else begin: no_gated_clock 57 assign the_clk = clk; 58 end 59 endgenerate 60 61 always @(posedge the_clk) begin 62 secret_accum_q <= secret_accum_q + accum_in + secret_value; 63 end 64 65 // Test combinatorial paths of different sizes 66 always @(*) begin 67 s1_out = s1_in; 68 s1up_out = s1up_in; 69 s2_out = s2_in; 70 s8_out = s8_in; 71 s64_out = s64_in; 72 s65_out = s65_in; 73 s129_out = s129_in; 74 s4x32_out = s4x32_in; 75 end 76 77 for (genvar i = 0; i < 3; ++i) begin 78 assign s6x16up_out[0][i] = s6x16up_in[0][i]; 79 assign s6x16up_out[1][i] = s6x16up_in[1][i]; 80 end 81 for (genvar i = 0; i < 4; ++i) begin 82 assign s8x16up_out[0][i] = s8x16up_in[0][i]; 83 assign s8x16up_out[1][i] = s8x16up_in[1][i]; 84 end 85 for (genvar i = 0; i < 8; ++i) begin 86 assign s8x16up_3d_out[i[2]][i[1]][i[0]] = s8x16up_3d_in[i[2]][i[1]][i[0]]; 87 end 88 89 90 sub sub (.sub_in(s33_in), .sub_out(s33_out)); 91 92 // Test sequential path 93 assign accum_out = secret_accum_q; 94 95 // Test mixed combinatorial/sequential path 96 assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q; 97 98 final $display("destroying %m"); 99 100endmodule 101 102module sub ( 103 input [32:0] sub_in, 104 output [32:0] sub_out); 105 106 /*verilator no_inline_module*/ 107 108 assign sub_out = sub_in; 109 110endmodule 111